Dr. Juan A. Montiel-Nelson Profile

Dr. Juan A. Montiel-Nelson

at Univ de Las Palmas de Gran Canaria

SPIE Involvement:

Author

Proceedings Article | 30 June 2005 Paper

A one-step algorithm for finding the optimum solution of the state justification problem in RTL designs using MILP

Hector Navarro, Juan Montiel-Nelson, Javier Sosa, Jose Garcia

Proceedings Volume 5837, (2005) https://doi.org/10.1117/12.608526

KEYWORDS: Logic, Clocks, Multiplexers, Binary data, Digital electronics, Logic devices, Lanthanum, Electronic design automation, Computer programming, Switches

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Proceedings Article | 30 June 2005 Paper

A CMOS latched driver using bootstrap technique for low-voltage applications

Jose Garcia, Juan Montiel-Nelson, Saeid Nooshabadi

Proceedings Volume 5837, (2005) https://doi.org/10.1117/12.608300

KEYWORDS: Logic, Transistors, Picosecond phenomena, Capacitance, Capacitors, Lanthanum, Power supplies, CMOS technology, Switching, Device simulation

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Proceedings Article | 30 June 2005 Paper

Statistically optimized VLSI architecture for buffer for EBCOT in JPEG2000 encoder

Amit Gupta, Saeid Nooshabadi, Juan Montiel-Nelson

Proceedings Volume 5837, (2005) https://doi.org/10.1117/12.608585

KEYWORDS: Very large scale integration, Computer programming, JPEG2000, Statistical analysis, Field programmable gate arrays, Clocks, Surface plasmons, Lanthanum, Optimization (mathematics), Wavelets

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Proceedings Article | 21 April 2003 Paper

System-level verification methodology for advanced switch fabrics

Javier Sosa, Juan Montiel-Nelson, Hector Navarro, Mahendra Shahdadpuri, Roberto Sarmiento

Proceedings Volume 5117, (2003) https://doi.org/10.1117/12.498612

KEYWORDS: Switches, Interfaces, Deep ultraviolet, C++, Telecommunications, Computer programming languages, Computer programming, Lanthanum, Product engineering, Microelectronics

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A system-level verification methodology for advanced switch fabrics is introduced in this paper. Verification is getting more time-consuming as design complexity increases and typically consumes over half of the design effort. Writing testbenches in an ad-hoc verification environment, such as Verilog, VHDL or in C/C++ using PLI directly, is tedious, unproductive and the reusability is low. Time-to-market is critical at chip-level verification, if we add the short life cycles and the changing standards, the design and verification of new products require new design and verification tools. As result of our methodology a verification framework is also presented. The decomposition of each interface of the switch fabric allows the reconfiguration of the framework, when there is a new revision of one design. This idea promotes the reuse of the main interface code and verification statements. The development of the verification framework in C++, 'e' and Verilog demonstrates that our methodology can be applied independently of the programming language. New features, added to the framework such as error insertion, give a highest control over the verification and they enhance the verification coverage in corner case mode. On the other hand, the golden reference layer is the key of the automatic mode, because a high level model can be used as reference to check the correctness of the DUV automatically and the synchronization issues are resolved between the different simulator natures. Several commercial and non-commercial advanced switch fabrics have been verified using this method. The highest complexity verified circuits were VSC882/VSC872 (GigaStream Chip Set). The usefulness of the proposed methodology is demonstrated by GigaStream Chip Set functional success and the saving of a 60% in the verification time per effort unit. In general, given a programming language, the improvement of using our methodology is around a 40% in verification time per effort unit.

Proceedings Article | 21 April 2003 Paper

Macromodel for exact computation of propagation delay time in GaAs and CMOS technologies

Jose Garcia, Juan Montiel-Nelson, Javier Sosa, Hector Navarro, Roberto Sarmiento

Proceedings Volume 5117, (2003) https://doi.org/10.1117/12.498586

KEYWORDS: Gallium arsenide, Differential equations, Transistors, Numerical analysis, Logic, Field effect transistors, Capacitance, Computer simulations, Switching, Fluctuations and noise

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Proceedings Article | 21 April 2003 Paper

VESTA: a system-level verification environment based on C++

Mahendra Shahdadpuri, Javier Sosa, Héctor Navarro, Juan Montiel-Nelson, Roberto Sarmiento

Proceedings Volume 5117, (2003) https://doi.org/10.1117/12.498618

KEYWORDS: C++, Logic, Lanthanum, Excel, Binary data, Head, Complex systems, Systems modeling, Telecommunications, Human-machine interfaces

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Proceedings Article | 21 April 2003 Paper

High-performance VLSI architecture for video processing

Hector Navarro, Juan Montiel-Nelson, Javier Sosa, Jose Garcia, Roberto Sarmiento, Saeid Nooshabadi

Proceedings Volume 5117, (2003) https://doi.org/10.1117/12.498585

KEYWORDS: Very large scale integration, Image processing, C++, Clocks, Raster graphics, Roentgenium, Video processing, Image filtering, Video, Mathematical morphology

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Proceedings Article | 21 November 2001 Paper

ATM over SDH: design of a STM-16c transceiver using GaAs technology

Oscar Tubio, Roberto Esper-Chain, Francisco Gonzalez, Felix Tobajas, Valentin de Armas, Juan Montiel-Nelson, Roberto Sarmiento

Proceedings Volume 4591, (2001) https://doi.org/10.1117/12.449153

KEYWORDS: Asynchronous transfer mode, Transceivers, Clocks, Gallium arsenide, Logic, Standards development, Error control coding, Field effect transistors, Logic devices, System on a chip

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Showing 5 of 8 publications

SPIE Conference Volume | 21 April 2003

VLSI Circuits and Systems

Conference Committee Involvement (2)

VLSI Circuits and Systems II

9 May 2005 | Sevilla, Spain

VLSI Circuits and Systems

19 May 2003 | Maspalomas, Gran Canaria, Canary Islands, Spain

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