Unmanned Aerial Vehicle (UAV) can carry various types of visual sensors, and the image information it collects can be applied to visual tasks such as target localization and target recognition. This paper proposes a geometric analysis target positioning algorithm based on IMU-LK optical flow based on the image information collected by UAV visual sensors, and the experimental results show that compared with the traditional geometric analysis target positioning algorithm, the geometric analysis target positioning algorithm based on IMU-LK optical flow has a better target positioning accuracy, and it can be adapted to the demand of real-time passive positioning in complex environments.
Most previous studies on visual adversarial attacks mainly pay close attention to the attack performance but only few of them concerns the appearance of the examples after the generated adversarial perturbation been exerted on. Without enforcing any restrictions over the adversarial perturbation often leads to conspicuous and attention-grabbing patterns in the generated adversarial examples which can be easily identified by humans. In order to address the issue mentioned above, we propose a method to craft the perturbation generated by visual adversarial attack for object recognition through leveraging the post-hoc visual explanation methods for DNNs to generate saliency map️ which are capable of indicating the region of the input image that makes the most important contribution to the model prediction. Through pointing out the region where the adversarial attack should focus on to maximize the impact and confining the scope of adversarial perturbation to be exerted, our method can generate natural looking adversarial examples while maintaining high attack performance. With extensive experiments in which the method proposed in this work is compared to the current state-of-the-art adversarial attack techniques all of which are applied to widely used deep neural networks on standard datasets, the results show that our proposed method produces significantly more realistic and natural looking adversarial examples than several state-of-the-art baselines while achieving competitive attack performance.
KEYWORDS: Convolution, Field programmable gate arrays, Digital signal processing, Windows, Object detection, Design, Convolutional neural networks, Computer hardware, Detection and tracking algorithms, Deep learning
Most deep learning models for object detection are designed based on convolutional neural networks, requiring powerful computing and storage capabilities typically provided by hardware platforms such as GPUs and CPUs. In contrast, FPGAs offer low power consumption and strong computational capabilities; however, deploying neural network models directly on FPGA embedded platforms is challenging. To address these issues, this paper takes the YOLO-V3 target detection algorithm as an example, introducing the hierarchical structure of the YOLO-V3 network, analyzing acceleration methods for each layer in the YOLO-V3 network, designing a convolutional neural network accelerator, and comparing its performance with that of GPUs. The designed accelerator effectively utilizes FPGA hardware computing resources, achieving an overall average performance of 192.229 GOP/s.
As an important part of semiconductor manufacturing, wafer defect detection has been studied more and more. With the gradual maturity of computer technology, image processing based detection methods have been widely used in wafer defect detection. However, there are still many problems to be solved in semiconductor wafer defect detection under complex background. Therefore, a wafer defect detection method based on adaptive multi-scale optical flow detection is designed in this paper. The principle of optical flow detection is applied to defect detection. The horizontal difference between the graph to be identified through optical flow detection, which an well tolerate the difference caused by the defect types existing on the wafer can be effectively identified. Experimental results show that the proposed method can effectively improve the signal-to-noise ratio of wafer defect detection.
In optoelectronic systems, infrared target tracking is a critical function. Due to occlusion causing template drift in infrared target tracking, correlation filtering algorithms have poor performance for infrared targets. Although target trackers based on Siamese convolutional neural networks exhibit excellent tracking performance, their complex architecture and high computational complexity hinder their real-time application on embedded chips. Furthermore, the output of anchor-based trackers is often unstable, which can be detrimental to the closed-loop control of optoelectronic devices. Therefore, this paper proposes a tracker based on the Siamese network for infrared small target tracking and presents an innovative lightweight approach to enhance real-time performance while minimizing accuracy loss. With regards to different backbone network structures, the computational complexity required for embedded computing was initially analyzed. Subsequently, artificial intelligence interpretability methods were employed to assess the performance of distinct networks, select the optimal backbone network, and ultimately striking a balance between accuracy and speed. Ultimately, real-time operation is achieved on embedded devices.
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