KEYWORDS: Design and modelling, Power consumption, Picosecond phenomena, Computer hardware, Mathematical optimization, Data processing, Signal processing, Data conversion, Clocks, Logic
Among the four basic operations, the division has a high level of technical complexity in implementation, so the design of a hardware divider generally becomes a key and difficult point in the design of data processing units. Based on practical needs, combined with new theories and practical developments in the field of divider design, this article implements an integer divider with improved pre-processing modules that can reduce computational cycles. It adopts the SRT-4 algorithm, selects the minimum redundant form for the remainder, uses on-the-fly conversion method for quotient calculation, and is supplemented by minimal hardware logic to form a data path. The focus is on low-cost, low-power, minimalist, and modular design. This design implements division function and then uses software to complete simulation verification. Under the standard process unit of 90 nm, the comprehensive area of this design is 15576 𝜇𝑚2 , power consumption 4.1326 mW, delay 790 ps compared to traditional dividers without improvement, the overall performance improvement is as high as 47%~82%.
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