As device size continues to shrink, stochastic-induced roughness of resist features exposed by photolithography is of increasing concern to the semiconductor industry. In this paper, we propose an end-to-end approach for line roughness analysis by using the Line Roughness Module from our CDU solution family, which is a part of HMI’s metrology SEM tool the eP5. Simulated Scanning Electron Microscope (SEM) images of line/space patterns are used to verify the ability of the Module to reliably extract roughness related metrics. A set of imec EUV ADI images collected on our metrology SEM tool are analyzed by the Line Roughness Module, and wafer signature maps of various roughness metrics are obtained. These wafer maps not only help to analyze different roughness contribution sources, but also provide insights about feature roughness in a systematic way. Such information can be further used in a feedback loop to the scanner for model correction and process control.
Scanner induced pattern shifts between layers are a large contributor to DRAM Bitline to Active overlay. One of the main root causes for this Pattern Shift non-Uniformity are lens aberrations. Currently measuring the Bitline to Active overlay requires a decap CDSEM method1. In this paper, an in-resist pattern shift uniformity metrology method is proposed which quantifies the main DRAM Bitline to Active overlay without the necessity to decap. We have designed a high transmission reticle (≥ 60%) to measure the pattern shift non-uniformity between two dense gratings under the rotation angle of the Active layer in both cold and hot lens states. Each module on the reticle contains product-like features and a variety of metrology targets, i.e. alignment and overlay, such that the product-to-product and the productto- metrology pattern shift fingerprints can be measured. OPC is applied to enlarge the overlapping process windows of the metrology targets with respect to the product-like features.
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