Due to non-ideal optical effects such as aberration and optical diffraction, printed poly gates on the wafer suffer from
across-gate linewidth variation (AGLV) and across-chip linewidth variation (ACLV,) especially in the subwavelength
regime. The poly gate distortion affects device electrical characteristics, including drive current (Ion), leakage current
(Ioff), and threshold voltage (Vt). For circuits sensitive to layout, such as compact memory cells, electrical performances
can vary with image distortion of each transistor even after applying resolution enhancement technologies (RETs) such
as optical proximity corrections. In this paper, we demonstrate the impact of OPC settings on the performance of 6T-SRAM
cells. The printed transistor gate and active region patterns are simulated by an in-house OPC engine. The device
model for each distorted transistor is then extracted based on approximating each distorted channel pattern with a set of
smaller rectangles. Consequently, Electrical performance such as static noise margin (SNM) can be obtained by
incorporating these extracted device models into a circuit simulator. Preliminary results show that OPC settings such as
segmentation length and numbers of corrections can affect wafer image quality and electrical performance in different
ways.
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