Mr. Meng-Hsiu Wu Profile

Meng-Hsiu Wu

at United Microelectronics Corp

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Publications (1)

Proceedings Article | 15 May 2007 Paper

Implementation of double dipole lithography for 45-nm node poly and diffusion layer manufacturing with 0.93NA

Meng-Hsiu Wu, Michael Hsu, Stephen Hsu, Bo-Jou Lu, Yung-Feng Cheng, Yueh-Lin Chou, Chuen-Huei Yang

Proceedings Volume 6607, 660731 (2007) https://doi.org/10.1117/12.729020

KEYWORDS: Photomasks, Critical dimension metrology, Optical proximity correction, Semiconducting wafers, Resolution enhancement technologies, Lithography, Manufacturing, Calibration, Data modeling, Printing

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The double dipole lithography (DDL) has been proven to be one of the resolution enhancement technologies for 45 nm node. In this paper, we have implemented a full-chip DDL process for 45nm node using ArF immersion lithography. Immersion exposure system can effectively enlarge the process DoF (depth of focus). Combining with dipole illumination can help us to reach smaller k1 value (~0.31) and meet the process requirements of poly and diffusion layers on 45nm node by using only 0.93 NA exposure tool. However, from a full-chip processing point of view, the more challenging question should be: how to calibrate a good model from two exposure and decompose original design to separate mask sets? Does the image performance achieve a production worthy standard? At 45nm node, we are using one-fourth of the exposure wavelength for the patterning; there is very little room for error. For DDL full-chip processing, we need a robust application strategy to ensure a very tight CD control. We implemented an integrated RET solution that combines DDL along with polarization, immersion system, and model based OPC to meet full-chip manufacturing requirement. This is to be a dual-exposure mask solution for 45nm node - X-dipole exposure for vertical mask and horizontal for Y-dipole. We show a process design flow starting from the design rule analysis, layout decomposition, model-based OPC, manufacturing reliability check, and then to the mask data preparation. All of the work has been implemented using MaskWeaver^TM geometry engine. Additionally, we investigated printability for through-pitch line features, ASIC logic, and SRAM cell design patterns. Different circuit layout needs dedicated special OPC treatment. To characterize the related process performance, we use mask enhancement error factor (MEEF), process window (PW), and critical dimension uniformity (CDU) to analyze the simulation data. Since we used the tri-tone Att-PSM, the mask making flow and spec was also taking into consideration. The device electrical performance was examined for production feasibility. We conclude that the DDL process is ready for 45nm node and is well within reach to be used on next generation production environment.

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