As semiconductor process design rules continue to shrink, the ability of optical inspection tools to separate between true
defects and nuisance becomes more and more difficult. Therefore, monitoring Defect of Interest (DOI) become a real
challenge (Figure 1). This phenomenon occurs due to the lower signal received from real defects while noise levels remain
almost the same, resulting in inspection high nuisance rate, which jeopardizes the ability to provide a meaningful, true
defect Pareto. A non-representative defect Pareto creates a real challenge to a reliable process monitoring (Figure 4).
Traditionally, inspection tool recipes were optimized to keep data load at a manageable level and provide defect maps with
~10% nuisance rate, but as defects of interest get smaller with design rule shrinkage, this requirement results in a painful
compromise in detection sensitivity. The inspection is usually followed by defect review and classification using scanning
electron microscope (SEM), the classification done manually and it is performed on a small sample of the inspection defect
map due to time and manual resources limitations. Sample is usually 50~60 randomly selected locations, review is
performed manually most of the times, and manual classification is performed for all the reviewed locations.
In the approach described in this paper, the inspection tool recipe is optimized for sensitivity rather than low nuisance rate
(i.e. detect all DOI with compromising on a higher nuisance rate). Inspection results with high nuisance rate introduce new
challenges for SEM review methodology & tools. This paper describe a new approach which enhances process monitoring
quality and the results of collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and
GLOBALFOUNDRIES® utilizing Applied Materials ADRTrueTM & SEMVisionTM capabilities.
The study shows that the new approach reveals new defect types in the Pareto, and improves the ability to monitor the
process and identify excursion for low magnitude defect of interest.
Immersion lithography addresses the limits of optical lithography by providing higher NA's (NA > 1),
which enable imaging of smaller features and hence it enables production of 45nm logic devices. One of
the key challenges of this advanced technology, however, is controlling the defectivity level produced
specifically by the Lithography immersion stepper and track systems. To control and monitor the
immersion processes in production, consideration has been given to identifying an alternative to the
traditional sensitivity approaches, using Darkfield (DF) and Brightfield (BF) wafer inspection
methodologies. This unique method should provide for stable, reliable and sensitive inspection results
which are capable of supporting a technology node introduction (product ramp) as well as monitoring the
base line performance (in other words, capture excursions).
The following study was done to explore laser DUV Brightfield inspection, utilizing the Applied Materials
UVisionTM, which has the ability to detect defects as small as 20-40nm size. Additionally a joint project
between AMD, ASML and AMAT developed an appropriate inspection strategy that combines,
lithographic defect printing simulations and sensitive inspection routines to identify defect problems
effectively, drive defect reduction efforts and result in stable production monitoring. We investigated the
use of traditional Photo Test Monitor (PTM) as a valid technique to monitor the introduction of the
immersion lithography at 45nm. In addition, we explored the correlation between these PTM wafers and
the actual production wafers for new types of defects. It was found that the amount of small protrusion
defects (~20-40nm size) increased on immersion PTM wafers compared to dry processed PTM wafers.
Based on process experiments at AMD and immersion defect simulations provided by ASML we were able
to isolate immersion specific defect problems from general lithography related defects also seen in Dry
lithography. The results show that unique combination of high sensitivity defect inspection methods and
simulation efforts can very effectively drive defect reduction efforts and accelerate yield on advanced
technology like immersion lithography. Additionally, it is also possible to provide a production monitoring
of 45nm immersion processes with such extreme sensitive inspection of PTM wafers of defects down to
20nm.
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