Mr. Ming-Chien Chiu Profile

Ming-Chien Chiu

at Powerchip Semiconductor Manufacturing Corp

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Publications (2)

Proceedings Article | 29 March 2013 Paper

Capability study and challenges to sub-2x nm node contact hole patterning

Wan-Lin Kuo, Ya-Ting Chan, Meng-Feng Tsai, Yi-Shiang Chang, Chia-Chi Lin, Ming-Chien Chiu, Chun-Hsun Chen, Hung-Ming Wu, Mao-Hsing Chiu

Proceedings Volume 8682, 86821G (2013) https://doi.org/10.1117/12.2011434

KEYWORDS: Etching, Chemical reactions, Scanning electron microscopy, Optical lithography, Image processing, Double patterning technology, Photoresist processing, Lithography, Photomasks, Process control

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Proceedings Article | 4 December 2008 Paper

Challenges of 29nm half-pitch NAND Flash STI patterning with 193nm dry lithography and self-aligned double patterning

M. C. Chiu, Benjamin Szu-Min Lin, M. F. Tsai, Y. S. Chang, M. H. Yeh, T. H. Ying, Chris Ngai, Jaklyn Jin, Stephen Yuen, Sem Huang, Yongmei Chen, Liyan Miao, Kevin Tai, Amiad Conley, Ian Liu

Proceedings Volume 7140, 714021 (2008) https://doi.org/10.1117/12.804685

KEYWORDS: Etching, Double patterning technology, Lithography, Optical lithography, Line width roughness, Manufacturing, Scanners, Semiconducting wafers, Line edge roughness, 193nm lithography

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High NA (1.35) Immersion litho runs into the fundamental limit of printing at 40-45nm half pitch (HP). The next generation EUVL tool is known to be ready not until year 2012. Double patterning (DP) technology has been identified as the extension of optical photolithography technologies to 3xnm and 2xnm half-pitch for the low k1 regime to fill in the gap between Immersion lithography and EUVL. Self Aligned Double Patterning (SADP) Technology utilized mature process technology to reduce risk and faster time to market to support the continuation of Moore's Law of Scaling to reduce the cost/function. SADP uses spacer to do the pitch splitting bypass the conventional double patterning (e.g. Litho-Freeze-Litho-Etch (LFLE), or Litho-Etch-Litho-Etch (LELE)) overlay problem. Having a tight overlay performance is extremely critical for NAND Flash manufacturers to achieve a fast yield ramp in production. This paper describes the challenges and accomplishment of a Line-By-Spacer (LBS) SADP scheme to pattern the 29nm half-pitch NAND Flash STI application. A 193nm Dry lithography was chosen to pattern on top of the amorphous carbon (a-C) film stack. The resist pattern will be transferred on the top a-C core layer follow by spacer deposition and etch to achieve the pitch splitting. Then the spacer will be used to transfer to the bottom a-C universal hardmask. This high selectivity a-C hardmask will be used to transfer the 29nm half-pitch pattern to the STI. Good within wafer CD uniformity (CDU) <2nm and line width roughness (LWR) <2nm for the 29nm half-pitch NAND FLASH STI were demonstrated as the benefits using double amorphous carbon hardmask layers. The relationships among the photoresist CDs, CD trimming , as-deposited spacer film thickness, spacer width and the final STI line/core space/gap space CDs will also be discussed in this paper since patterning is combining both lithography performance with CVD and Etch process performance. Film selection for amorphous carbon and the complete DP hardmask scheme in terms of etching selectivity, optical properties and stress optimization was another key challenge to balance excellent litho alignment signal strength and straight pattern profiles without line bending effects. Etching efforts also played a very important roll to obtain pattern integrality under such a high aspect ratio (> 10) case through the whole SADP process. Finally, cost analysis for 193nm dry lithography SADP will be compared to 193nm Immersion lithography SADP.

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