Power delivery represents a key challenge in scaled technology nodes as interconnect wiring resistance increases and design constraints impact how much wiring can be used for power distribution. Here, we discuss several methodologies, including both pre-PDK and post-PDK, to benchmark the integrity of power delivery network designs with advanced technology features such as vertical FET (VTFET) transistor architecture, skip-level vias, buried power rails and backside power delivery. For a post-2nm node VTFET architecture, we employ a pre-PDK benchmarking to find that buried power rails can reduce gate delay by as much as 30%. For 5nm and 2nm technology nodes, we use existing PDKs to simulate backside power delivery networks (BS-PDN) and find that scaled logic area can be reduced by 10-30% while minimum-pitch interconnect RC delay can be reduced by as much as 70% depending on reference design.
Vertical-Transport (VTFET) Nanosheet Technology is an attractive solution to enable aggressive CMOS scaling in the sub-45nm contact-gate-pitch (CGP) regime. By decoupling the classic tradeoff of S/D contacts, gate length & contact-gate-pitch (CGP), VTFET technology overcomes middle-of-the-line (MOL) dominated performance pinch-points by providing independent optimization of the contact dimension & device width as well as significant effective capacitance (Ceff) reduction [1]. VTFET offers an attractive solution at sub-45nm CGP, however it introduces unique design challenges that need to be optimized to take full power-performance-area (PPA) entitlement. In this paper, we present for the first time a logic standard cell architecture to enable a competitive VTFET technology. First, we introduce key features of the VTFET architecture which enable significant advantages relative to leading-edge competitive technologies. Further we describe key Design Technology Co-Optimization (DTCO) scaling knobs that naturally lend themselves to VTFET such as single fins, buried power rails and gate-contact super vias can achieve competitive area scaling vs. an industry 7nm lateral FinFET transistor reference. Finally, we draw conclusions of overall PPA benefits of this technology.
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