In this work, we demonstrate our first-principles based methodology to include atomistic level simulations to evaluate the promise of different metals on the performance of MOL/BEOL interconnects. The specific metals that we focus on include Cu, Ru (both fcc and hcp), Co, and Mo where the conductivity of these metals, including the degradation from grain boundaries extracted from ab initio simulations, is included in a parasitic field solver and subsequently used to extract the interconnect parasitics of standard cells. Lithography considerations are addressed through simulations of patterned, “real” wires. PPA is evaluated through simulations of an 128x128 SRAM memory array where we find significant improvement in the read and write delay of 20% and 40%, respectively when we replace M1 with Ru(fcc).
KEYWORDS: Systems modeling, Fin field effect transistors, Logic, TCAD, Standards development, Signal generators, Resistance, Metals, Materials processing, Field effect transistors
In this paper, we describe a framework to enable the memory array simulations for Materials to Systems CooptimizationTM (MSCOTM) flows. The methodology is applied for projected 3 nm logic FinFET technology node SRAM array. To form the SRAM array, a “tiling” approach is utilized, where neighbor cells are created by copying and mirroring the first cell. Then this process is repeated to create the rest of the array. Electrical pulses are applied to the word-line and bit-line to activate the read and write operations. We demonstrate 128 ×128 SRAM array simulations and find that the farthest cell from the word-line driver is vulnerable.
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