Dr. Ruben Salvador Profile

Dr. Ruben Salvador

Teaching Assistant at Univ Politécnica de Madrid

SPIE Involvement:

Author

Area of Expertise:

Reconfigurable Computing , Evolvable Hardware , Adaptive Embedded Systems , Digital Signal Processing , FPGAs

Websites:

Company Website

Publications (4)

Proceedings Article | 5 October 2017 Paper

Parallel exploitation of a spatial-spectral classification approach for hyperspectral images on RVC-CAL

R. Lazcano, D. Madroñal, H. Fabelo, S. Ortega, R. Salvador, G. Callicó, E. Juárez, C. Sanz

Proceedings Volume 10430, 104300A (2017) https://doi.org/10.1117/12.2279613

KEYWORDS: Hyperspectral imaging, Image classification, Image processing, Principal component analysis, Algorithm development, Machine learning, Parallel processing

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Proceedings Article | 3 May 2011 Paper

Bio-inspired FPGA architecture for self-calibration of an image compression core based on wavelet transforms in embedded systems

Rubén Salvador, Alberto Vidal, Félix Moreno, Teresa Riesgo, Lukáš Sekanina

Proceedings Volume 8067, 806704 (2011) https://doi.org/10.1117/12.887123

KEYWORDS: Wavelets, Image compression, Discrete wavelet transforms, Image processing, Field programmable gate arrays, Calibration, Evolutionary algorithms, Embedded systems, Wavelet transforms, Image filtering

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Proceedings Article | 28 May 2009 Paper

Approach to an FPGA embedded, autonomous object recognition system: run-time learning and adaptation

Rubén Salvador, Carlos Terleira, Félix Moreno, Teresa Riesgo

Proceedings Volume 7363, 736312 (2009) https://doi.org/10.1117/12.821687

KEYWORDS: Object recognition, Field programmable gate arrays, Neural networks, Computer architecture, Very large scale integration, Current controlled current source, Pattern recognition, Network security, Control systems, Network architectures

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Proceedings Article | 10 May 2007 Paper

Architectural design for a low cost FPGA-based traffic signal detection system in vehicles

Ignacio López, Rubén Salvador, Jaime Alarcón, Félix Moreno

Proceedings Volume 6590, 65900M (2007) https://doi.org/10.1117/12.721694

KEYWORDS: Field programmable gate arrays, Neural networks, Signal detection, Image processing, Neurons, Digital filtering, Logic devices, Image filtering, Clocks, Safety

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Conference Committee Involvement (1)

VLSI Circuits and Systems VI

24 April 2013 | Grenoble, France

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