In today’s advanced semiconductor process manufacturing, critical dimensions of device features have decreased to a few nanometers while the aspect ratios have increased beyond 100. The cost of process development has significantly increased and the performance of the lithography and plasma etch patterning processes are critical to the success of ramping a new technology node toward profitable high-volume manufacturing. In this paper, a three-dimensional Monte Carlo-based feature scale model, ProETCH®, has been developed for modeling etch process with the capability of optimizing the process by solving forward and inverse problems. The shallow trench isolation etch process in self-aligned double patterning was investigated. The mechanism of silicon etch by Ar/Cl2 plasma was developed with experimental data as a reference. The developed model captures the trends and has quantitative accuracy in comparison to the experimental data, and can be used to identify the different fundamental pathways which contribute to the profile metrics. The developed model was then used to solve the forward problem, which is to predict profiles at different process conditions, and the inverse problem, which is to search for the process conditions (e.g, power and pressure) which could result in desirable profiles.
Emerging memory technologies such as Resistive Memory (RRAM) have gained a lot of attention to meet the requirements of a potential analog computing element, due to its non-volatile characteristics, scalability and energy efficiency. An RRAM device typically consists of a resistive switching layer (e.g. HfO2) sandwiched between two metal electrodes. Since oxygen vacancies are critical to the functioning of the device, it is desirable to achieve residue free etching using oxygen-less plasmas, and preferably minimize exposure to ambient environment. In this work, we discuss the RRAM patterning challenges and their impact on the device characteristics including the switching/forming voltage.
Within the world of integrated circuit manufacturing there is a continuous effort to increase device density in order to improve speed, performance and costs. Current technology is driving a transition from devices that use a planar transistor to a more “3D” design, such as with nanowires or even vertically oriented transistors. The fabrication of nanowire devices demonstrates a good example of 3D etch challenges where both anisotropic and highly selective isotropic etch processes are needed. Alternating Si and SiGe layers are first etched vertically, then are later recessed selective to one another. There are a number of literature reports which have demonstrated the capability of recessing SiGe selective to Si, however the opposite is not as well established. The key challenges of this task are maximizing the selectivity to the SiGe layers as well as any other spacer and mask materials exposed on the wafer including SiO2, Si3N4, SiOCN and SiBCN. In this work, we present a study of isotropic etching for Si selective to SiGe in CF4/O2/N2 and NF3/O2/N2 based plasmas with selectivities higher than 50:1 achieved. Potential selectivity mechanisms are based on preferential oxidation of mixed SiGe layers opposed to Si, while formation of the NO molecule can result in excessive oxide layer removal from the Si surface.1,2 A qualitative model is put forth to describe the resulting etch profiles using this chemistry. Supporting data regarding F:O ratio, temperature, and Si layer thickness dependency are shown in efforts to support the model. These results will provide essential insight as the industry decides which process solution is optimal for GAA devices.
Multi-layer patterning schemes involve the use of Silicon containing Anti-Reflective Coating (SiARC) films for their anti-reflective properties. Patterning transfer completion requires complete and selective removal of SiARC which is very difficult due to its high silicon content (>40%). Typically, SiARC removal is accomplished through a non-selective etch during the pattern transfer process using fluorine containing plasmas, or an ex-situ wet etch process using hydrofluoric acid is employed to remove the residual SiARC, post pattern transfer. Using a non-selective etch may result in profile distortion or wiggling, due to distortion of the underlying organic layer. The drawbacks of using wet etch process for SiARC removal are increased overall processing time and the need for additional equipment. Many applications may involve patterning of active structures in a poly-Si layer with an underlying oxide stopping layer. In such applications, SiARC removal selective to oxide using a wet process may prove futile. Removing SiARC selectively to SiO2 using a dry etch process is also challenging, due to similarity in the nature of chemical bonds (Si – O) in the two materials.
In this work, we present highly selective etching of SiARC, in a plasma driven by a surface wave radial line slot antenna. The first step in the process involves an in-situ modification of the SiARC layer in O2 plasma followed by selective etching in a NF3/H2 plasma. Surface treatment in O2 plasma resulted in enhanced etching of the SiARC layer. For the right processing conditions, in-situ NF3/H2 dry etch process demonstrated selectivity values greater than 15:1 with respect to SiO2. The etching chemistry, however, was sensitive to NF3:H2 gas ratio. For dilute NF3 in H2, no SiARC etching was observed. Presumably, this is due to the deposition of ammonium fluorosilicate layer that occurs for dilute NF3/H2 plasmas. Additionally, challenges involved in selective SiARC removal (selective to SiO2, organic and Si layers) post pattern transfer, in a multi-layer structure will be discussed.
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