Dr. Tae Kwon Jee Profile

Dr. Tae Kwon Jee

Founder, CEO at Crossait

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Publications (8)

Proceedings Article | 10 April 2024 Presentation + Paper

Real time EPE measurement as a yield correlated metrology on advanced DRAM nodes

Taekwon Jee, Joonsang You, Hong-Goo Lee, Seungmo Hong, Jonghoi Cho, Taeseop Lee, Jong-hyun Seo, Michael Shifrin, Ronnie Porat, Amir Rosen, Rohit Kumar Singh, Jeong-Ho Yeo, Younghoon Kim, Jun Park, Byung-Jo Lim, Chan-Hee Kwak

Proceedings Volume 12955, 129550P (2024) https://doi.org/10.1117/12.3010813

KEYWORDS: Overlay metrology, Critical dimension metrology, Metrology, Semiconducting wafers, Stochastic processes, Time metrology, Design, Data modeling, Process control, Optical lithography

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The Edge Placement Error (EPE) is growing concerns due to the complexity increases of process variation as the design rule shrinkage of DRAM device. The EPE is a well-accepted metric which can be derived from CD, Overlay and LER measurements from more than patterning layers that concerned. Therefore, real time EPE measurement becomes a major factor to monitor and control the pattern fidelity. The pattern fidelity could be found from the edge placement measurement as a distance to design intent as possible without pattern defects. However, the traditional application of photolithography and etch biases according to a design rule or model for identifying pattern fidelity has inherent low TMU, multiple non consistence data sources and time-consuming off-line analysis. In previous works, we demonstrated the innovative e-Beam EPE metrology application using All-In-One (AIO) methodology to comply the required Total Measurement Uncertainty (TMU) and Time to Result (TTR) on the advanced DRAM nodes. AIO imaging and analysis methodology that deconvolute CD, overlay and relevant EPE metrics from a single see-through image is the most important differentiation for this EPE analysis approach. The in-cell direct EPE measurement with All-In-One (AIO) imaging and massive sampling demonstrates the better process controls and monitoring from the co-optimization of multiple control parameters and direct measurement of the yield relevant metrics. In this paper, we would like to show a couple of EPE monitoring use cases which shows good correlation to the final yield map through the massive and multi-layer measurements. Especially, it is expected that the EPE component which measures the edge-to-edge distance between different features of multi-layers can be a useful indicator for predicting yield along with CD and overlay. To investigate the local and random variabilities, which local stochastic effects are contained, we also studied the degree of yield prediction of the EPE component with increasing number of measurement sites in local area. It is proposed that using a large amount of measurement sites allows to improve the yield prediction accuracy to a certain extent, which means the local stochastic effects can be effectively analyzed with the use of massive metrology approach. In addition, from the prediction accuracy study using EPE model-based machine learning, we proved that the EPE is sufficiently sensitive indicator to capture potential yield-loss problems in normal wafer, as well. Therefore, in-line EPE monitoring using AIO metrology enables the root-cause analysis of patterning weak points and provides a better process monitoring/correction solution to enable faster advanced DRAM node development ramp and high-volume stability.

Proceedings Article | 27 April 2023 Poster + Paper

Large field of view metrology: detecting critical edge placement error signatures not seen with small field of view in an HVM environment

Mohamed Ridane, Ivy Chen, Jaden Song, Peter Nikolsky, Kuan-Ming Chen, Shinyeong Lee, Sean Park, Kolos Lin, Yu-Chi Su, Kyoyeon Cho, Ethan Yu, James Park, Abdalmohsen Elmalk, Chih-Hung Hsieh, Alexander Serebryakov, Lei Zhang, Taekwon Jee, Joonsang You, Hong-Goo Lee, Jongmin Park, Jungchan Kim, Sang-Woo Kim, Seungmo Hong, Jaewook Seo

Proceedings Volume 12496, 124963C (2023) https://doi.org/10.1117/12.2659692

KEYWORDS: Metrology, Semiconducting wafers, High volume manufacturing, Line width roughness, Critical dimension metrology, Scanning electron microscopy, Optical lithography, Environmental sensing, Edge detection, Overlay metrology

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Proceedings Article | 13 June 2022 Presentation

Evaluation of robust EPE monitoring and control metric methodologies for advanced DRAM nodes yield improvement

Yaniv Abramovitz, Jeong-Ho Yeo, Taekwon Jee, Hong-Goo Lee, Sang-Ho Lee, Chan-Ha Park

Proceedings Volume PC12053, PC120530N (2022) https://doi.org/10.1117/12.2613931

KEYWORDS: Overlay metrology, Image processing, Yield improvement, Metrology, Line edge roughness, Process control, Critical dimension metrology, Scanning electron microscopy, Optical lithography, Inspection

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Proceedings Article | 22 February 2021 Presentation + Paper

Edge placement error wafer mapping and investigation for improvement in advanced DRAM node

Kuan-Ming Chen, Wolfgang Henke, Ji-Hoon Jung, Ewa Kasperkiewicz, Anita Bouma, Rizvi Rahman, Gratiela Isai, Gwang-Gon Kim, Sotirios Tsiachris, Jae-Doug Yoo, Yuna Park, JaeYoung Park, Jonggeun Won, Nang-Lyeom Oh, Hsin-Yu Chen, WeiTai Lin, Chih-Hung Hsieh, Kuo-Feng Pao, Kyoyeon Cho, Abdalmohsen Elmalk, Sudharshanan Raghunathan, Taekwon Jee, Seung-Uk Jeong, Jeongwoo Jae, Sang-Woo Kim, Dongyoung Lee, Jungchan Kim, WonKwang Ma, Sang-Ho Lee, Chan-Ha Park

Proceedings Volume 11611, 116111V (2021) https://doi.org/10.1117/12.2584149

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Overlay metrology, Optical lithography, Metrology, Visualization, Statistical analysis, Lithography, Graphic design, Etching

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Proceedings Article | 20 March 2018 Presentation + Paper

Co-optimization of exposure dose and etch process for SAQP pitch walk control

Mark John Maslow, Vadim Timoshkov, Ton Kiers, Tae Kwon Jee, Liesbeth Reijnen, Kaushik Kumar, Marc Demand, Carlos Fonseca, Florin Cerbu, Guillaume Schelcher, Christophe Beral

Proceedings Volume 10587, 1058704 (2018) https://doi.org/10.1117/12.2297345

KEYWORDS: Etching, Semiconducting wafers, Lithography, Diffractive optical elements, Plasma, Optical lithography, Atomic layer deposition, Critical dimension metrology, Image processing, Deposition processes

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Spacer-assisted pitch multiplication is a patterning technique that is used on many different critical layers for memory and logic devices. Pitch walk can occur when the spacer process, a combination of lithography, deposition and etch processes, produce a repeating, non-uniform grating of space / line CDs. It has been shown that for spacer-assisted double patterning (SADP), where the lithography pitch is doubled, pitch walk can be reduced by controlling the exposure dose such that the uniformity of the final SADP spaces defined by the core resist mandrel (S1) is balanced with the final SADP space defined by the distance between adjacent SADP lines (S2). For higher pitch multiplications, starting with spacer-assisted quadruple patterning (SAQP) reducing systematic pitch walk with exposure dose becomes more complex.

Co-optimization of the lithography and etch processing is expected to be required to achieve the best pitch walk control. Previous work has shown that improving the across wafer CD uniformity of the line patterns after core etch has limited impact on the space CD uniformity after the SADP process, whereas the CD uniformity of the spaces after SAQP did show some dependence. There are additional space populations created by an SAQP process. The variation of these different populations, along with the spacer deposited line populations, is the root cause of the non-uniform grating that results in pitch walk. The complex interactions of the lithography and etch processes’ impact on the CD and profile need to be understood to produce the optimal performance.

Pitch walk is a component of the overall Edge Placement Error (EPE) budget. With current nodes using SAQP for multiple device layers and future nodes expected to continue to implement this patterning technique, minimization of pitch walk variability is an important part of overall patterning optimizations. In this work, we will show how cooptimized exposure dose and etch processes for SAQP patterning can improve pitch walk performance. We will provide a target exposure dose metric for a 32nm pitch SAQP grating. The methodology for achieving the best pitch walk performance by combination of etch process optimization with dose correction will also be shown.

Proceedings Article | 13 March 2018 Paper

EUV via hole pattern fidelity enhancement through novel resist and post-litho plasma treatment

Hidetami Yaegashi, Kyohei Koike, Carlos Fonseca, Fumiko Yamashita, Kumar Kaushik, Shinya Morikita, Kiyohito Ito, Shota Yoshimura, Vadim Timoshkov, Mark Maslow, Tae Kwon Jee, Liesbeth Reijnen, Peter Choi, Mu Feng, Chris Spence, Stijn Schoofs

Proceedings Volume 10586, 1058605 (2018) https://doi.org/10.1117/12.2297661

KEYWORDS: Extreme ultraviolet, Optical lithography, Plasma treatment, Stochastic processes, Extreme ultraviolet lithography, Photomasks, System on a chip, Lithography, Silica, Manufacturing

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Proceedings Article | 16 October 2017 Presentation + Paper

EUV local CDU healing performance and modeling capability towards 5nm node

Tae Kwon Jee, Vadim Timoshkov, Peter Choi, David Rio, Yu-Cheng Tsai, Hidetami Yaegashi, Kyohei Koike, Carlos Fonseca, Stijn Schoofs

Proceedings Volume 10450, 1045017 (2017) https://doi.org/10.1117/12.2281627

KEYWORDS: Etching, Optical proximity correction, Stochastic processes, Critical dimension metrology, Extreme ultraviolet, Metrology, Photoresist processing, Performance modeling, Error analysis

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Proceedings Article | 21 March 2017 Presentation + Paper

Co-optimization of lithographic and patterning processes for improved EPE performance

Mark Maslow, Vadim Timoshkov, Ton Kiers, Tae Kwon Jee, Peter de Loijer, Shinya Morikita, Marc Demand, Andrew Metz, Soichiro Okada, Kaushik Kumar, Serge Biesemans, Hidetami Yaegashi, Paolo Di Lorenzo, Joost Bekaert, Ming Mao, Christophe Beral, Stephane Larivière

Proceedings Volume 10149, 101490N (2017) https://doi.org/10.1117/12.2257979

KEYWORDS: Semiconducting wafers, Photoresist processing, Source mask optimization, Overlay metrology

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Complimentary lithography is already being used for advanced logic patterns. The tight pitches for 1D Metal layers are expected to be created using spacer based multiple patterning ArF-i exposures and the more complex cut/block patterns are made using EUV exposures. At the same time, control requirements of CDU, pattern shift and pitch-walk are approaching sub-nanometer levels to meet edge placement error (EPE) requirements. Local variability, such as Line Edge Roughness (LER), Local CDU, and Local Placement Error (LPE), are dominant factors in the total Edge Placement error budget. In the lithography process, improving the imaging contrast when printing the core pattern has been shown to improve the local variability. In the etch process, it has been shown that the fusion of atomic level etching and deposition can also improve these local variations. Co-optimization of lithography and etch processing is expected to further improve the performance over individual optimizations alone.

To meet the scaling requirements and keep process complexity to a minimum, EUV is increasingly seen as the platform for delivering the exposures for both the grating and the cut/block patterns beyond N7. In this work, we evaluated the overlay and pattern fidelity of an EUV block printed in a negative tone resist on an ArF-i SAQP grating. High-order Overlay modeling and corrections during the exposure can reduce overlay error after development, a significant component of the total EPE. During etch, additional degrees of freedom are available to improve the pattern placement error in single layer processes.

Process control of advanced pitch nanoscale-multi-patterning techniques as described above is exceedingly complicated in a high volume manufacturing environment. Incorporating potential patterning optimizations into both design and HVM controls for the lithography process is expected to bring a combined benefit over individual optimizations. In this work we will show the EPE performance improvement for a 32nm pitch SAQP + block patterned Metal 2 layer by cooptimizing the lithography and etch processes. Recommendations for further improvements and alternative processes will be given.

Showing 5 of 8 publications

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