The design and implementation of a smart image sensor to provide high dynamic range and pixel level digital
image processing is described. In this article we investigate important issues in the development of digital
intelligent pixel CMOS image sensors. We have developed a high density imager with pixel level stochastic
arithmetic and a high dynamic range exceeding 90 db. The ASIC prototype named PIKASSO includes a 96×64
pixel array, each pixel has a fill factor of 15% in an area of 29×29 μm2. The average power consumption per
pixel at a frequency of 150 kHz is 78 μW.
KEYWORDS: Signal processing, Image enhancement, Image processing, Digital signal processing, Very large scale integration, Image quality, Video, RGB color model, Edge detection, Cameras
In this paper an image enhancing technique is described. It is based on Shunting Inhibitory Cellular Neural Networks. As the limitation of the linear approaches to image coding, enhancement, and feature extraction became apparent, research in image processing began to disperse into the three goal-driven directions. However SICNNs model simultaneously addresses the three problems of coding, enhancement, and extraction as it acts to compress the dynamic range, reorganize the signal to improve visibility, suppress noise, and identify local features. The algorithm we are describing is simple and cost-effective, and can be easily applied in real-time processing for digital still camera application.
KEYWORDS: Neural networks, Image processing, Image enhancement, Very large scale integration, Data processing, Visual process modeling, Computer architecture, Computer simulations, Neurons, Chemical elements
Shunting inhibition is a model of early visual processing which can provide contrast and edge enhancement, and dynamic range compression. An architecture of digital Shunting Inhibitory Cellular Neural Network for real time image processing is presented. The proposed architecture is intended to be used in a complete vision system for edge detection and image enhancement. The present hardware architecture, is modeled and simulated in VHDL. Simulation results show the functional validity of the proposed architecture.
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