Defectivity control continues to challenge advanced semiconductor manufacturing, especially immersion lithography
processes. Immersion exposure tools are sensitive to incoming wafer defects, including top coat voids, surface defects,
and other random or systematic anomalies. A single defective wafer could contaminate the exposure tool's immersion
hood resulting in lengthy and costly repairs. To mitigate this problem, TEL developed an integrated and real-time macro
inspection solution to identify defective wafers which could potentially damage immersion exposure tools. The Wafer
Intelligent Scanner (WIS) module integrates within the CLEAN TRACKTM LITHIUS ProTM platform without impacting
footprint or throughput. By utilizing user defined inspection criteria, wafers can be inspected prior to and after exposure
for macro defects. Wafers failing to meet inspection criteria prior to exposure are automatically re-routed to bypass the
exposure tool and subsequent process modules.
Micron Technology, Inc., explores the challenges of defining specific wafer sampling scenarios for users of
multiple integrated metrology modules within a Tokyo Electron Limited (TEL) CLEAN TRACKTM LITHIUSTM. With
the introduction of integrated metrology (IM) into the photolithography coater/developer, users are faced with the
challenge of determining what type of data is required to collect to adequately monitor the photolithography tools and
the manufacturing process. Photolithography coaters/developers have a metrology block that is capable of integrating
three metrology modules into the standard wafer flow. Taking into account the complexity of multiple metrology
modules and varying across-wafer sampling plans per metrology module, users must optimize the module wafer
sampling to obtain their desired goals. Users must also understand the complexity of the coater/developer handling
systems to deliver wafers to each module. Coater/developer systems typically process wafers sequentially through each
module to ensure consistent processing. In these systems, the first wafer must process through a module before the next
wafer can process through a module, and the first wafer must return to the cassette before the second wafer can return to
the cassette. IM modules within this type of system can reduce throughput and limit flexible wafer selections. Finally,
users must have the ability to select specific wafer samplings for each IM module. This case study explores how to
optimize wafer sampling plans and how to identify limitations with the complexity of multiple integrated modules to
ensure maximum metrology throughput without impact to the productivity of processing wafers through the
photolithography cell (litho cell).
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.