This paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. It allows to estimate the probabilities of physical open defects occurrences in a cell, describes its faulty behavior caused by the defects and finds the test sequences that detect those faults. Finally, the minimal set of test sequences is selected to cover all detectable faults and the optimal complex test sequence is constructed. Experimental results for cells from industrial standard cell library are presented as well.
KEYWORDS: Satellite navigation systems, Signal processing, Global Positioning System, Digital signal processing, Navigation systems, Electronic filtering, Field programmable gate arrays, Modulation, Satellites, Boxcar filters
A variety of currently operational GNSS frequencies and rapid development of new navigation satellite systems resulted
in the need for interoperability and compatibility. Recent state-of-the-art integrated GNSS front-ends are capable of
simultaneous support of multiple navigation systems [1, 2]. A unification of the signal processing part is also possible
and, what is more, desirable. This paper introduces a proposal for universal instruction set extension (ISE), which is used
for accelerating signal processing in SDR (Software Defined Radio) based GNSS applications. The results of this work
were implemented and tested on the chip multithreading general purpose processor – AGATE [3], running on the Xilinx
Virtex-6 ML605 FPGA evaluation board.
This paper presents a new architecture of a charge pump voltage converter. The charge pump implements novel parasitic
capacitances precharge control loop. Output voltage ripples are significantly reduced.
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