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The era of EUV technology is approaching and use of EUV lithography in chip manufacturing process was reported. The EUV technology has still serious challenges to overcome, to which belong defectivity, source power and throughput of the exposure tool, to name the most obvious. Important part of the lithography, which differs significantly from previous optical technology, is the mask. The mask stack, especially the multilayer (ML) mirror surface and its protection is of high importance, determining the reflectivity of the mask. The ML mirror is protected by a thin Ru capping layer, which however is very sensitive to oxidation and damage during mask manufacturing processes and its use.[1] Also estimation of the capping layer thickness is not trivial, and is unreliable by damage free analytical methods. In our work, we focus on the capping layer integrity and assess it as function of several applied cleaning processes. The integrity is examined via e-beam repair process and AFM measurement of the feature height. As identified in previous experiments, the UV exposure used in manufacturing processes has significant influence on the Ru layer at some conditions. However, there is good chance to find conditions at which the Ru layer is not attacked by the UV exposure, and removed by the subsequent wet process in which the products of Ru oxidization are diluted. Above mentioned procedure we intend to identify EUV mask manufacturing conditions, at which the capping layer is not impacted by the clean process. At the end of the manufacturing process, the EUV mask has to have a thick enough capping layer to perform the repair process and protect the ML mirror during the mask lifetime. Currently available processes allow us to manufacture EUV masks with a remaining capping layer up to five times thicker than required for the e-beam mask repair. This result confirms readiness of the mask manufacturing process for HVM from perspective of the mask health and integrity of the ML mirror and Ru capping layer.
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