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18 February 2022 High-efficiency vector and scalar fused load store unit design
Wentao Ma, Libo Huang, Lin Deng, Yuanhu Cheng, Ling Yang, Gan Tong, Run Yan, Mengqiao Lan, Jing Zhang, Weixia Xu
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Proceedings Volume 12162, International Conference on High Performance Computing and Communication (HPCCE 2021); 121621A (2022) https://doi.org/10.1117/12.2628136
Event: 2021 International Conference on High Performance Computing and Communication, 2021, Guangzhou, China
Abstract
An efficient vector and scalar fused load store unit (VS-LSU) is designed under the open source RISC-V framework. It can support vector access instructions of different addressing modes. Compared with scalar units, it reduces the number of instructions while increasing the memory access speed. Through the fusion of vectors and scalars, the growth of port and buffer overhead is effectively controlled. The experimental results show that when the same number of memory access operations are completed, the 256-bit VS-LSU reduces the number of instructions executed by 75%, and the memory access speed increases by 72.1% than the scalar unit; the fusion optimization reduces the overhead in port signal and buffer by more than 90% compared to the conventional vector unit, and the overall performance has been significantly improved.
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Wentao Ma, Libo Huang, Lin Deng, Yuanhu Cheng, Ling Yang, Gan Tong, Run Yan, Mengqiao Lan, Jing Zhang, and Weixia Xu "High-efficiency vector and scalar fused load store unit design", Proc. SPIE 12162, International Conference on High Performance Computing and Communication (HPCCE 2021), 121621A (18 February 2022); https://doi.org/10.1117/12.2628136
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KEYWORDS
Signal processing
Data processing
Data storage
Logic
Data acquisition
Data fusion
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