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30 April 2023 Scaling physically aware logic diagnosis to complex high volume designs
Brian Archer
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Proceedings Volume 12495, DTCO and Computational Patterning II; 1249514 (2023) https://doi.org/10.1117/12.2660201
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States
Abstract
Logic diagnosis attempts to identify defects within an Integrated Circuit (IC) using only a logical model of the design with no knowledge of the physical layout. With the ever-increasing size and complexity of ICs, limitations associated with traditional logic-based diagnostics have made it less effective at determining root causes for failing die. To provide increased a
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Brian Archer "Scaling physically aware logic diagnosis to complex high volume designs", Proc. SPIE 12495, DTCO and Computational Patterning II, 1249514 (30 April 2023); https://doi.org/10.1117/12.2660201
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KEYWORDS
Logic
Diagnostics
Integrated circuit design
Integrated circuits
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