Physical design level PPA evaluation of buried power rail at 2nm node

Giuliano Sisto; Odysseas Zografos; Pieter Weckx; Geert Hellings; Julien Ryckaert

doi:10.1117/12.2656337

28 April 2023 Physical design level PPA evaluation of buried power rail at 2nm node

Giuliano Sisto, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert

Proceedings Volume 12495, DTCO and Computational Patterning II; 124951X (2023) https://doi.org/10.1117/12.2656337
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States

Conference Poster

Abstract

The backside of the silicon substrate is predicted to be heavily exploited by the next generation of integrated circuits to fulfill the increasingly challenging task of delivering current to billions of transistors. The buried power rail presented in this paper represents an enticing way to start transitioning from the frontside to the backside by moving the power rails in the silicon substrate. This is achieved by leveraging the large portions of Shallow Trench Isolation between fin-based devices. A metal layer is added to a conventional BEOL stack to enable this technology in commercial EDA tools for physical implementation and IR drop analysis. A comprehensive PPA evaluation of the buried power rail is performed at the block level, using a 64-bit CPU block and imec A14 nanosheet PDK. Typical physical design parameters are varied in the process to understand the impact of buried power rail in different conditions. The results show performance improvements both in iso-target (from 2% to 3.5%) and maximum frequency (from 9.5% to 12%). Both stem from a 7% shorter wirelength and 16% smaller area. From the IR drop perspective, better results are obtained with the buried rails showing a reduction up to 33% and enabling the use of sparser power delivery structures. This paper shows how moving the power rails to the substrate represents a powerful block-level knob for power delivery network optimization and as a performance booster.

Citation Download Citation

Giuliano Sisto, Odysseas Zografos, Pieter Weckx, Geert Hellings, and Julien Ryckaert "Physical design level PPA evaluation of buried power rail at 2nm node", Proc. SPIE 12495, DTCO and Computational Patterning II, 124951X (28 April 2023); https://doi.org/10.1117/12.2656337

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