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In FinFET transistors, the parasitic capacitance between the source/drain contact and the metal gate tends to be high, and this can negatively impact device performance. Adding a metal gate recess step can reduce capacitance, but unfortunately it also increases the metal gate resistance. By changing the metal gate recess profile, a good balance between resistance and capacitance can be achieved to reduce RC. In this work, we investigate FinFET metal gate recess profile settings and how changes in profile settings affect FinFET resistance and parasitic capacitance (R and C). Metal gate recess dimensional changes and profile changes can modify parasitic capacitance and impact electrical performance. We performed a virtual DOE where we varied the gate CD, recess depths, and metal gate recess profiles to understand the impact of these changes on FinFET resistance, capacitance, and electrical performance. Different recess profiles, such as sharp head and antenna shapes, were simulated using SEMulator3D® virtual process fabrication and pattern dependence modeling. Subsequent electrical analysis was performed to extract resistance and capacitance values and to model device transistor behavior. We replicated the process to calculate the resistance and capacitance for a GAAFET, and investigated performance trends during changes in gate CD, tungsten (W) etchback and recess profile variations.
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