The image restoration algorithms based on time-frequency domain computation is high maturity and applied widely in
engineering. To solve the high-speed implementation of these algorithms, the TFDC hardware architecture is proposed.
Firstly, the main module is designed, by analyzing the common processing and numerical calculation. Then, to improve
the commonality, the iteration control module is planed for iterative algorithms. In addition, to reduce the computational
cost and memory requirements, the necessary optimizations are suggested for the time-consuming module, which
include two-dimensional FFT/IFFT and the plural calculation. Eventually, the TFDC hardware architecture is adopted
for hardware design of real-time image restoration system. The result proves that, the TFDC hardware architecture and
its optimizations can be applied to image restoration algorithms based on TFDC, with good algorithm commonality,
hardware realizability and high efficiency.
Efficient algorithm for blind image deconvolution and its high-speed implementation is of great value in practice.
Further optimization of SeDDaRA is developed, from algorithm structure to numerical calculation methods. The main
optimization covers that, the structure's modularization for good implementation feasibility, reducing the data
computation and dependency of 2D-FFT/IFFT, and acceleration of power operation by segmented look-up table. Then
the Fast SeDDaRA is proposed and specialized for low complexity. As the final implementation, a hardware system of
image restoration is conducted by using the multi-DSP parallel processing. Experimental results show that, the
processing time and memory demand of Fast SeDDaRA decreases 50% at least; the data throughput of image restoration
system is over 7.8Msps. The optimization is proved efficient and feasible, and the Fast SeDDaRA is able to support the
real-time application.
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