EUV (extreme ultraviolet) lithography is progressively being inserted in high volume manufacturing of semiconductors to keep up with node shrinkage. However, defectivity remains one big challenge to address in order to be able to exploit its full potential. As in any type of lithographic process, processing failures and in-film particles are contributors that need to be reduced by the optimization of coating and development processes and improved dispense systems. On top of these defects, stochastic failures, due to photon shot noise or non-uniformities in the resist, are another major contribution to the defectivity. To support their mitigation, etch process can be used to avoid their transfer to underlying layers. However, it requires a sufficient resist mask thickness. For line and space patterns, providing more resist budget comes with a trade-off which is the increase of pattern collapse failures, especially with shrinking critical dimensions. Collapse mitigation approaches are therefore very important to enable tight pitches and were explored. Stack engineering and especially optimization of resist under layers will be crucial components to enable patterning and defect reduction of shrinking pitches. Finally, as an alternative to traditional chemically amplified resists, metal containing resists are also promising because of their inherent high etch resistance. Dedicated hardware and processes were developed the use of such materials and prevent metal contamination to other tools during further processing steps.
In this report will be presented the latest solutions to further decrease defectivity towards manufacturable levels and provide more process margin to achieve better quality patterning towards the limits of NA 0.33 EUV exposure. Furthermore, technologies to improve CD uniformity and stability, which are required for mass production, will also be reported.
Extreme ultraviolet (EUV) lithography faces major challenges for smaller nodes due to the impact of stochastic and processing failures.1 One of the main challenges for pitch shrink at these nodes is the optimization of the trade-off between break type defects versus bridge type defects as the process window between these defect modes gets smaller.2 In this paper, we examine EUV defect reduction techniques for Chemically Amplified Resist (CAR) and Metal Oxide Resist (MOR) via coater/developer process development combined with optimized etching processes.
For extreme ultraviolet lithography (EUVL), resist mask pattern height is limited by resist line pattern collapse. High aspect ratio patterns improve resist roughness performance and provide more etch resistance to allow a wider margin of etch transfer. However, the high aspect ratio patterns tend to induce pattern collapse easily. In the past, many works have focused on the reduction of capillary force to mitigate pattern collapse. These methods employ low surface tension rinse and optimization of developer process. However, other factors can also influence pattern collapse. Another important parameter causing pattern collapse is the low adhesion force between the resist and underlayer. In this work, we investigate the adhesion properties between resist and underlayer materials. Materials screened were spin-on SiARC, organic BARC, SiC as well as CVD SiON. In addition, two adhesion treatments were used for the underlayers to change the surface properties. Each underlayer material was evaluated on a criteria of pattern collapse limit CD and process window. Adhesion between resist and underlayer is discussed by using adhesive work. The adhesive work was calculated from surface free energy and found to have good correlation with pattern collapse limitting CD. As an application of the improved adhesive work, a resist film thickness was increased to achieve higher aspect ratio (AR) patterns. While the reference pattern was limited by collapse at an AR of 1.2, with the improved adhesion, an AR of 2.1 was achieved. The knowledge gained in this work will be especially useful for 5 nm and smaller nodes.
The enhancement in chemical gradients between the EUV exposed and unexposed areas can generate a wider process window, possibly, a smaller stochastic defectivity, and a lower local CD uniformity in EUV resists. This enhancement, in turn, helps to overcome the challenge of the small process window in high NA EUV lithography. In this work, a new concept resist, which is developed based on our chemical gradient enhancement technique model, is used to drive the chemical gradient upward chemically. The resist also has the capability of absorbing UV selectively at EUV exposed areas. Therefore, the UV flood exposure system, which has been discussed in Photosensitized Chemically Amplified ResistTM (PSCARTM), is used as another key part to further enhance the new resist. The new concept resist with UV lights was confirmed to give 15.1% improvement in its EUV sensitivity and, simultaneously, 25.0% improvement in local CD uniformity. This technique might be one of the solutions to bring CAR resist further into high-NA EUV lithography.
EUV (extreme ultraviolet) lithography has recently begun to be applied to semiconductor mass production, and it is expected that more layers will be applied in the future. In particular, the adoption of EUV is a great advantage in that the number of masks required for ArF immersion lithography can be reduced, which can reduce not only the cost but also the risk of EPE (edge placement error) due to superposition. However, the pattern defects of EUV lithography is still issue, and its high resolution performance has not been fully exploited. In order to further pattern shrink of semiconductors in the future, a major issue is how to reduce these defects.
In this report, we introduce the latest approach for mitigation the defects of EUV lithography patterns. The defects are confirmed not only ADI (after development inspection) but also AEI (after etch inspection).
Flood Exposure Assisted Chemical Gradient Enhancement Technology (FACET) is introduced for improvement in EUV resist resolution, process control, roughness, patterning failure and sensitivity. Experimental EUV exposure latitude was enhanced (~1.5 times) with FACET using the assist of UV flood exposure. The mechanism of the process window improvement by FACET is explained by non-linear resist coloring (enhancement of UV absorption) vs. EUV exposure dose to enhance acid image contrast during UV flood exposure. To balance chemical gradient enhancement and stochastic effects, Stochastic Aware Resist Formulation and Process optimizer (SARF-Pro) with a fast stochastic simulation model is created. SARF-Pro predicts stochastic patterning failure risks, and optimizes resist formulation and processes by putting emphasis on stochastic variation across patterns. Photosensitized Chemically Amplified ResistTM (PSCARTM) 2.0 with FACET and standard chemically amplified resist (CAR) optimized in SARF-Pro suggests that PSCAR 2.0 with FACET has the potential of better process window, roughness, sensitivity and, we hypothesize, reduced risk of stochastic defects compared with standard CAR.
Although being progressively introduced to mass production, extreme ultraviolet (EUV) lithography still faces major challenges for 5nm and smaller nodes due to the impact of stochastic and processing failures, resulting in very narrow defect process windows. 1 These failures are strongly linked to critical dimension (CD) variations.2 Therefore, careful control of CD is now directly linked to defect reduction in addition to more conventional in-film particles/developer residues reduction. Photoresist profiles are also believed to be one possible limiting factor and improvements via collapse control or increased resist mask thickness for etch transfer need to be considered. In this paper, most recent understandings regarding defect process window limitations and optimization of processes to further enable narrow pitch EUV lithography will be presented.
CD-based process windows have been an analysis workhorse for estimating and comparing the robustness of semiconductor microlithography processes for more than 30 years. While tolerances for variation of CD are decreasing in step with the target CD size, the acceptable number of printed defects has remained flat (Hint: Zero) as the number of features increases quadratically. This disconnect between two key process estimators, CD variability and defect rate, must be addressed. At nodes that require EUV lithography, estimating the printed defects based solely on a Mean CD (“Critical Dimension”) process window is no longer predictive. The variability / distribution of the printed CDs must be engineered so that there are no failures amongst the billions of instances, rendering the Mean CD, often measured on just hundreds or thousands of instances, a poor predictor for outliers. A “defect-aware” process window, where the count of printed defects is considered in combination with more advanced statistical analysis of measured CD distributions can provide the needed predictability to determine whether a process is capable of sufficient robustness. Determining process robustness where stochastics and defects are taken into account can be simplified by determining the CD process margin. In this work we study dense contact hole arrays exposed with 0.33NA single exposure EUV lithography after both the lithography and etch steps. We describe a methodology for expanding the analysis of process windows to include more than the mean and 3σ of the data. We consider the skew and kurtosis of the distribution of measured CD results per focus-exposure condition and compare / correlate the measured CD process window results to the CD process margin.
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