This paper presents a 14-bit column-parallel two-step compact hybrid ADC for low-power digital IRFPA application, with the area and speed performances compromise. The proposed two-step ADC works in two phases: in the first phase, A 7-bit SAR ADC performs the coarse quantization; in the second phase, a 7-bit SS ADC further performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, and the main clock of fine SS ADC can be reduced to 50MHz at the sampling rate of 238 kS/s. More importantly, by sharing analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are reduced consequently. The proposed two-step ADC is designed in 0.18 μm standard CMOS process. The simulation results show that the proposed two-step ADC has a differential nonlinearity of −0.87/+0.43 LSB and an integral nonlinearity of −0.86/+0.71 LSB. The layout of the proposed ADC can be implemented in the pixel pitch less than 10 μm. The conversion time is 4.2 μs, and the power consumption of each column ADC is only 65 μW with a 3.3V power supply. The simulation results indicate the proposed two-step ADC is suitable for low-power digital readout circuits in the small pixel pitch IRFPA.
Region of Interest (ROI) readout is used in readout integrated circuit (ROIC) to improve the frame rate, and reduce the bandwidth for image sensor and infrared Focal Plane Array (IRFPA). The scheme of gray code addressing with the 64×1 minimum size of ROI is widely used. However, the circuit needs to be custom redesigned when the pixel array is changed, which reduces the scalability. The pixel scheme reduces the minimum size of ROI to 1×1. Because of its repeatable circuit design, the scheme has good scalability. But this program occupies the area of pixels, which reduces the dynamic range of image. In this paper, a ROI readout scheme using unit circuit for IRFPA is presented. The minimum size of ROI is reduced to 1×1 in the scheme without occupying the area of pixel. In order to achieve high scalability, reusable circuit named unit circuit is used to control the gating of pixels. The circuit design and simulation results are presented in this paper.
In a digital infrared focal plane array (IRFPA) thermal imager, imaging circuit has requirements of receiving serial data from digital FPA correctly and stably. Conventional data receiving method has disadvantages of low speed, low stability and poor adaptability, which results from clock synchronization difficulty at high data rate and unfixed serial link delay. A novel data receiving method basing on deserializer and sequence detection is proposed. Benefiting from the deserializer, high speed sampling can be implemented, and clock synchronization difficulty is lowered down. With sequence detection, not only the beginning of data packet but also the best sampling point can be correctly determined, even though an uncertain serial link delay exists. The proposed method has been implemented in FPGA achieving a single channel data receiving rate up to 550Mbps. Shaking table testing is completed which fully verifies the high stability and good adaptability of the proposed method.
This paper presents a logarithmic response burst mode IRFPA ROIC with pixel level integration of BDI structure and memory cells. BDI structure provides stable bias for the detector, and converts detector current into logarithmic voltage fast. On-chip high speed video record is achieved by high speed sampling the logarithmic response voltage and storing it into the memory cells in order. A column level SAR ADC is used to convert the outputs of memory cells into digital code. The prototype chip with 64×64 pixels was designed and fabricated. Ultra-high speed video capturing at 1Mfps with 100 consecutive frames is successfully demonstrated.
This paper presents a two-step ADC architecture for dual band infra-red focal plane array (IRFPA). It has advantages of small pixel area and low power over conventional pixel level ADC while maintaining the characteristic of enhancing well capacity of ROIC. The proposed two-step ADC with 16 bits is designed for middle / long wave (MW/LW) dual band IRFPA: 10-bit pulse frequency modulation (PFM) based pixel level ADC with 6-bit column paralleled Successive Approximation Register (SAR) ADC is employed for LW detector and 6-bit PFM based pixel level ADC with 10-bit column paralleled SAR ADC is employed for MW detector. Layout area of the pixel is 30 μm × 30 μm. The simulation result shows the DNL of the proposed two-step ADC for LW detector and MW detector are 0.6 LSB and 0.9 LSB respectively.
Digital readout integrated circuit (ROIC) has become the development tendency of ROIC for infrared focal plane array (IRFPA) due to its advantages such as improved ability of resisting interference, high readout rate and low readout noise. Compared with traditional analog ROIC, column-parallel analog-to-digital converters (ADCs) are integrated on digital ROIC. Because of the non-ideality of CMOS process, the column nonuniformity of digital ROIC is more obvious than that of analog ROIC due to device mismatch, which will lead to obvious column fixed pattern noise (FPN). In order to reduce column nonuniformity, the main sources of column nonuniformity in digital ROIC are analyzed firstly, including the mismatch between column analog readout channels, as well as ADCs. Then, analytical models have been developed to reveal the relationship between the column FPN and design parameters of digital ROIC. And the numerical computation with CMOS process parameters is implemented. The results show that the column FPN caused by digital ROIC can be reduced to less than 0.1% when the transistor area of tail current source in column analog readout channel is larger than 10μm2 and input transistor area of the first operational amplifier in ADC is larger than 20μm2 . By the help of the proposed mismatch model, column FPN of digital ROIC can be reduced over ten times with optimized design parameters, which provides beneficial guidance for digital ROIC design.
KEYWORDS: Synthetic aperture radar, Quantization, High dynamic range imaging, Signal to noise ratio, Readout integrated circuits, Amplifiers, Image sensors, Imaging systems
This paper presents a two-step ADC architecture for high dynamic range, high sensitivity image sensor. The proposed two-step ADC architecture works in two phases: the coarse quantization phase in each pixel, digital integration technique is applied to increase the well capacity as well as system’s dynamic range, and a capacitive transimpedence amplifier (CTIA) scheme is employed to achieve high sensitivity; The fine quantization phase in the column which reduces the bit width of the pixel-level ADC, pixel-level ADC’s noise and layout area are reduced consequently. The proposed two-step ADC with 18 bits is designed in 0.18 μm standard CMOS process. The optimized assignment for the bit width of pixel-level ADC and column paralleled ADC is applied. The simulation shows the signal to noise ratio (SNR) is 93.5 dB. The dynamic range is 108 dB. The least sensible electrons are 781 e-. The simulation results indicate the proposed twostep ADC is suitable for high dynamic range, high sensitivity image sensor.
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