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Digital readout integrated circuit (ROIC) has become the development tendency of ROIC for infrared focal plane array (IRFPA) due to its advantages such as improved ability of resisting interference, high readout rate and low readout noise. Compared with traditional analog ROIC, column-parallel analog-to-digital converters (ADCs) are integrated on digital ROIC. Because of the non-ideality of CMOS process, the column nonuniformity of digital ROIC is more obvious than that of analog ROIC due to device mismatch, which will lead to obvious column fixed pattern noise (FPN). In order to reduce column nonuniformity, the main sources of column nonuniformity in digital ROIC are analyzed firstly, including the mismatch between column analog readout channels, as well as ADCs. Then, analytical models have been developed to reveal the relationship between the column FPN and design parameters of digital ROIC. And the numerical computation with CMOS process parameters is implemented. The results show that the column FPN caused by digital ROIC can be reduced to less than 0.1% when the transistor area of tail current source in column analog readout channel is larger than 10μm2 and input transistor area of the first operational amplifier in ADC is larger than 20μm2 . By the help of the proposed mismatch model, column FPN of digital ROIC can be reduced over ten times with optimized design parameters, which provides beneficial guidance for digital ROIC design.
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