Region of Interest (ROI) readout is used in readout integrated circuit (ROIC) to improve the frame rate, and reduce the bandwidth for image sensor and infrared Focal Plane Array (IRFPA). The scheme of gray code addressing with the 64×1 minimum size of ROI is widely used. However, the circuit needs to be custom redesigned when the pixel array is changed, which reduces the scalability. The pixel scheme reduces the minimum size of ROI to 1×1. Because of its repeatable circuit design, the scheme has good scalability. But this program occupies the area of pixels, which reduces the dynamic range of image. In this paper, a ROI readout scheme using unit circuit for IRFPA is presented. The minimum size of ROI is reduced to 1×1 in the scheme without occupying the area of pixel. In order to achieve high scalability, reusable circuit named unit circuit is used to control the gating of pixels. The circuit design and simulation results are presented in this paper.
This paper presents a two-step ADC architecture for dual band infra-red focal plane array (IRFPA). It has advantages of small pixel area and low power over conventional pixel level ADC while maintaining the characteristic of enhancing well capacity of ROIC. The proposed two-step ADC with 16 bits is designed for middle / long wave (MW/LW) dual band IRFPA: 10-bit pulse frequency modulation (PFM) based pixel level ADC with 6-bit column paralleled Successive Approximation Register (SAR) ADC is employed for LW detector and 6-bit PFM based pixel level ADC with 10-bit column paralleled SAR ADC is employed for MW detector. Layout area of the pixel is 30 μm × 30 μm. The simulation result shows the DNL of the proposed two-step ADC for LW detector and MW detector are 0.6 LSB and 0.9 LSB respectively.
In a digital infrared focal plane array (IRFPA) thermal imager, imaging circuit has requirements of receiving serial data from digital FPA correctly and stably. Conventional data receiving method has disadvantages of low speed, low stability and poor adaptability, which results from clock synchronization difficulty at high data rate and unfixed serial link delay. A novel data receiving method basing on deserializer and sequence detection is proposed. Benefiting from the deserializer, high speed sampling can be implemented, and clock synchronization difficulty is lowered down. With sequence detection, not only the beginning of data packet but also the best sampling point can be correctly determined, even though an uncertain serial link delay exists. The proposed method has been implemented in FPGA achieving a single channel data receiving rate up to 550Mbps. Shaking table testing is completed which fully verifies the high stability and good adaptability of the proposed method.
This paper presents a logarithmic response burst mode IRFPA ROIC with pixel level integration of BDI structure and memory cells. BDI structure provides stable bias for the detector, and converts detector current into logarithmic voltage fast. On-chip high speed video record is achieved by high speed sampling the logarithmic response voltage and storing it into the memory cells in order. A column level SAR ADC is used to convert the outputs of memory cells into digital code. The prototype chip with 64×64 pixels was designed and fabricated. Ultra-high speed video capturing at 1Mfps with 100 consecutive frames is successfully demonstrated.
Digital infrared (IR) focal plan array (IRFPA) is one of the most significant characteristic of advanced IR imaging systems, it is implemented by integrating ADCs into the readout integrated circuit (ROIC). Successive Approximation Register (SAR) ADC is popular for column-level ADC architecture since it has low power and high resolution. In this paper a 14-bit RC hybrid SAR ADC with unary capacitor array is proposed, it has better linearity performance area compared with conventional SAR ADC. The proposed SAR ADC introduces resistor ladder for the last 6-bit conversion and it is shared by the whole SAR ADC array, so single SAR ADC’s layout’s length can be reduced, The proposed SAR ADC is designed in 130 nm standard CMOS process, the size of the SAR ADC core is 30 μm × 560 μm. the post simulation result show that its power consumption is 102 μW when the sampling rate is 100 kHz, and the worst DNL is 0.4 LSB when mismatching of 0.2% of capacitor array is introduced. The proposed SAR ADC suits for digital IRFPA applications.
Digital readout integrated circuit (ROIC) has become the development tendency of ROIC for infrared focal plane array (IRFPA) due to its advantages such as improved ability of resisting interference, high readout rate and low readout noise. Compared with traditional analog ROIC, column-parallel analog-to-digital converters (ADCs) are integrated on digital ROIC. Because of the non-ideality of CMOS process, the column nonuniformity of digital ROIC is more obvious than that of analog ROIC due to device mismatch, which will lead to obvious column fixed pattern noise (FPN). In order to reduce column nonuniformity, the main sources of column nonuniformity in digital ROIC are analyzed firstly, including the mismatch between column analog readout channels, as well as ADCs. Then, analytical models have been developed to reveal the relationship between the column FPN and design parameters of digital ROIC. And the numerical computation with CMOS process parameters is implemented. The results show that the column FPN caused by digital ROIC can be reduced to less than 0.1% when the transistor area of tail current source in column analog readout channel is larger than 10μm2 and input transistor area of the first operational amplifier in ADC is larger than 20μm2 . By the help of the proposed mismatch model, column FPN of digital ROIC can be reduced over ten times with optimized design parameters, which provides beneficial guidance for digital ROIC design.
KEYWORDS: Synthetic aperture radar, Quantization, High dynamic range imaging, Signal to noise ratio, Readout integrated circuits, Amplifiers, Image sensors, Imaging systems
This paper presents a two-step ADC architecture for high dynamic range, high sensitivity image sensor. The proposed two-step ADC architecture works in two phases: the coarse quantization phase in each pixel, digital integration technique is applied to increase the well capacity as well as system’s dynamic range, and a capacitive transimpedence amplifier (CTIA) scheme is employed to achieve high sensitivity; The fine quantization phase in the column which reduces the bit width of the pixel-level ADC, pixel-level ADC’s noise and layout area are reduced consequently. The proposed two-step ADC with 18 bits is designed in 0.18 μm standard CMOS process. The optimized assignment for the bit width of pixel-level ADC and column paralleled ADC is applied. The simulation shows the signal to noise ratio (SNR) is 93.5 dB. The dynamic range is 108 dB. The least sensible electrons are 781 e-. The simulation results indicate the proposed twostep ADC is suitable for high dynamic range, high sensitivity image sensor.
A high speed and high dynamic range digital ROIC for infrared FPA detectors is proposed. With using pixel-level ADC and parallel high speed transmission technology, frame rate and dynamic range of the digital ROIC is greatly improved. A 384×288 digital ROIC with pixel parallel charge packet counting ADCs and 4 parallel transmission channels is designed and fabricated using 0.11μm CMOS technology to verify the proposed ROIC architecture. With the proposed ROIC, a high speed high dynamic range infrared FPA detector is achieved with a frame rate of up to1000Hz and a dynamic range of up to 85dB.
In order to achieve high sensitivity for low-light-level CMOS image sensors (CIS), a capacitive transimpedance amplifier (CTIA) pixel circuit with a small integration capacitor is used. As the pixel and the column area are highly constrained, it is difficult to achieve analog correlated double sampling (CDS) to remove the noise for low-light-level CIS. So a digital CDS is adopted, which realizes the subtraction algorithm between the reset signal and pixel signal off-chip. The pixel reset noise and part of the column fixed-pattern noise (FPN) can be greatly reduced. A 256×256 CIS with CTIA array and digital CDS is implemented in the 0.35μm CMOS technology. The chip size is 7.7mm×6.75mm, and the pixel size is 15μm×15μm with a fill factor of 20.6%. The measured pixel noise is 24LSB with digital CDS in RMS value at dark condition, which shows 7.8× reduction compared to the image sensor without digital CDS. Running at 7fps, this low-light-level CIS can capture recognizable images with the illumination down to 0.1lux.
An incremental sigma-delta ADC is designed for column-parallel ADC array in CMOS image sensor. Sigma-delta modulator with single-loop single-bit structure is chosen for power consumption and performance reasons. Second-order modulator is used to reduce conversion time, without stability problem and large area accompanied by higher order sigma-delta modulator. The asymmetric current mirror amplifier used in integrator reduces more than 30% power dissipation. The digital filter and decimator are implemented by counters and adders with significantly reduced chip area and power consumption. A Clock generator is shared by 8 ADCs for trade-off among power, area and clock loading. The ADC array is implemented in a 0.18-μm CMOS technology and clocked at 10 MHz, and the simulated resolution achieves 15-bit with 255 clock cycles. The average power consumption per ADC is 118 μW including clock generator, and the area is only 0.0053 μm2.
A novel data transmission circuit for digital image sensors is presented. Large amounts of data are divided into m groups of n bits each. Each group of data is stored in an n-bit shift register. Under the control of a column scanner, at a time, only one group of data is selected to output serially to a common output line. Thus, as the scanner scans all the groups of data, the large amounts of data are serially output through the common line. A current-mode circuit transforms the output data into a low voltage swing signal which propagates over the common output line fast. A sense amplifier receives the low voltage swing signal and then recovers the full swing signal. Finally, a low-voltage differential signaling ( LVDS ) transmitter, which is fed with the full swing signal, transmits the data out chip. Because there is always only one of the m shift registers operating, the power consumption is greatly reduced. The simulation results show that the proposed circuit works correctly at a date rate of 400Mb/s. For n=14, and m=8, 32, 128, and 256, the power consumption of the prototype is as low as 1/4, 1/15, 1/50, and 1/80 that of the traditional serial link respectively.
CMOS image sensors (CIS) have lower power consumption, lower cost and smaller size than CCD image sensors. However, generally CCDs have higher performance than CIS mainly due to lower noise. The pixel circuit used in CIS is the first part of the signal processing circuit and connected to photodiode directly, so its performance will greatly affect the CIS or even the whole imaging system. To achieve high performance, CMOS image sensors need advanced pixel circuits. There are many pixel circuits used in CIS, such as passive pixel sensor (PPS), 3T and 4T active pixel sensor (APS), capacitive transimpedance amplifier (CTIA), and passive pixel sensor (PPS). At first, the main performance parameters of each pixel structure including the noise, injection efficiency, sensitivity, power consumption, and stability of bias voltage are analyzed. Through the theoretical analysis of those pixel circuits, it is concluded that CTIA pixel circuit has good noise performance, high injection efficiency, stable photodiode bias, and high sensitivity with small integrator capacitor. Furthermore, the APS and CTIA pixel circuits are simulated in a standard 0.18-μm CMOS process and using a n-well/p-sub photodiode by SPICE and the simulation result confirms the theoretical analysis result. It shows the possibility that CMOS image sensors can be extended to a wide range of applications requiring high performance.
KEYWORDS: Thermography, Imaging systems, Digital electronics, Sensors, Sun, Linear filtering, Signal detection, Infrared imaging, Infrared radiation, Digital imaging
Photo current integration is the key to improve the performance of a thermal imaging system. By integrating the photo
current in the capacitance, the signal-to-noise ratio of the system is greatly improved. Theoretically, the maximum
integration time of a thermal imaging system is the frame time of the system. However, due to the low well capacity of
the readout integrated circuit, the integration time of the photo current is often shorter than the frame time of the system.
To increase the well capacity of the readout circuit is one of the main research topics in thermal imaging system. The
super-framing technique can overcome the restriction by reading-out the detector signal in a rate higher than the frame
rate and then integrating the signal outside the IRFPA. As the signal integration is carried out outside the pixel, the
integration time is no longer restricted. The key of the super-framing technique is the transmission of the signal in high
readout rate. The digital readout circuit by integrating the analog-to-digital converter (ADC) array on the readout circuit
chip becomes more and more popular with the development of CMOS technologies. Since the digital signal can be
transferred outside the chip in a GS/s rate without any concern on noise and distortion, the super-framing technique
based on digital readout circuit is advantageous over the analog solution.
KEYWORDS: Digital electronics, Infrared imaging, Sensors, Imaging systems, Signal to noise ratio, Digital electronic circuits, Capacitors, Infrared radiation, Readout integrated circuits, Digital imaging
With the sustaining development of application requirements in infrared technology, modern infrared imaging system demands high frame rates, wide dynamic range, high spatial resolution and high sensitivity. Because it is impossible to integrate hundreds of pF capacitor in the limited area of detector pixel, the integration time of infrared staring imaging system will be restricted. Therefore, the underutilization of detector performance is unavoidable. Specially, long wave infrared detector must accommodate stronger infrared signal, and the integration capacitor is more easily saturated. For the sake of resolving the restriction of integration capacitor, an infrared image superframing technique based on high-speed digital transmission circuit is presented in this paper. Meanwhile, the mass raw data high-speed transmission from detector to imaging circuit is also capable via the proposed technique. With the usage of the technique, the signal to noise ratio (SNR) of infrared imaging system will be improved, and the dynamic range of infrared imaging system will be also extended. The theory analysis and results of simulation demonstrate that the proposed method is feasible and effective.
The readout integrated circuit (ROIC) is a bridge between the infrared focal plane array (IRFPA) and image processing circuit in an infrared imaging system. The ROIC is the first part of signal processing circuit and connected to detectors directly, so its performance will greatly affect the detector or even the whole imaging system performance. With the development of CMOS technologies, it’s possible to digitalize the signal inside the ROIC and develop the digital ROIC. Digital ROIC can reduce complexity of the whole system and improve the system reliability. More importantly, it can accommodate variety of digital signal processing techniques which the traditional analog ROIC cannot achieve. The analog to digital converter (ADC) is the most important building block in the digital ROIC. The requirements for ADCs inside the ROIC are low power, high dynamic range and small area. In this paper we propose an RC hybrid Successive Approximation Register (SAR) ADC as the column ADC for digital ROIC. In our proposed ADC structure, a resistor ladder is used to generate several voltages. The proposed RC hybrid structure not only reduces the area of capacitor array but also releases requirement for capacitor array matching. Theory analysis and simulation show RC hybrid SAR ADC is suitable for ADC array applications
The infrared imaging system has been developed for more than 50 years, from the early stage the scanned imaging
system using single unit detector to imaging system using focal plane detector arrays. For focal plane array detectors, the
readout circuit is used to read the photon detector signal out. Charge coupled device had been used for the readout of the
focal plane array detectors and currently CMOS technology is used. In this paper, readout circuit design using CMOS
technology for infrared focal plane array detectors is reviewed. As an interface between the detector and the image signal
processing circuits, readout circuit is a critical component in the infrared imaging system. With the development of the
CMOS technology, the readout circuit is now moving into the CMOS technology. With the feature size scaling down,
the readout cell size is reduced, which enable us to integrate more complex circuits into the readout cell. From the system
point of view, different requirements and specifications for the CMOS readout circuit are analyzed and discussed.
Different readout circuit parameters such as injection efficiency, dynamic range, noise, detector biasing control, power
consumption, unit cell area, etc are discussed in details. Performance specifications of different readout cell structures
are summarized and compared. Based on the current mirroring integration readout cell, a fully differential readout cell is
proposed. The injection efficiency of this proposed readout cell is very close to unity and the detector biasing voltage is
close to zero. Moreover, the dynamic range of the proposed readout cell is increased and the rejection on interference is
improved because of the fully differential structure. All these are achieved without much power consumption increasing.
Finally, a full digital readout circuit concept is introduced. By employing a current controlled oscillator, the photocurrent
is converted to frequency and integrated in digital domain and the final output is digital signal.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.