This paper presents a 14-bit column-parallel two-step compact hybrid ADC for low-power digital IRFPA application, with the area and speed performances compromise. The proposed two-step ADC works in two phases: in the first phase, A 7-bit SAR ADC performs the coarse quantization; in the second phase, a 7-bit SS ADC further performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, and the main clock of fine SS ADC can be reduced to 50MHz at the sampling rate of 238 kS/s. More importantly, by sharing analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are reduced consequently. The proposed two-step ADC is designed in 0.18 μm standard CMOS process. The simulation results show that the proposed two-step ADC has a differential nonlinearity of −0.87/+0.43 LSB and an integral nonlinearity of −0.86/+0.71 LSB. The layout of the proposed ADC can be implemented in the pixel pitch less than 10 μm. The conversion time is 4.2 μs, and the power consumption of each column ADC is only 65 μW with a 3.3V power supply. The simulation results indicate the proposed two-step ADC is suitable for low-power digital readout circuits in the small pixel pitch IRFPA.
With the development of science and technology, image sensors are more and more widely used, such as digital cameras and surveillance cameras. However, due to the physical characteristics of the photodetector, which performance is sensitive to the variation of the operating temperature. Therefore, a digital temperature sensor integrated on the chip is required to measure the operating temperature and assist in correction and compensation. Traditional scheme integrates one temperature sensor on the whole image sensor chip, which can’t reflect the temperature distribution for each pixel. It’s desirable to implement temperature measurement in pixel level for accurate correction, but existing temperature sensor occupying area of hundred μm2, which can’t be input to the pixel of image sensor. In additional, the power consumption of each temperature sensor is μW-level, which will dissipate considerable power for million temperature sensors. In this paper, a pixel-level integrated temperature sensor is proposed. The circuit is composed of only a capacitor and a conventional diode. The readout circuit is similar to that of the active pixel of image sensor, thus the ADC (Analog-to-Digital Converter) and other readout circuits and be multiplexed. The temperature sensor integrated in pixel is designed, which area is only 0.21 μm2. The simulation results show the increased power consumption for 50Hz working pixels don’t exceed 4%. It’s confirmed that the proposed pixel-level integrated temperature sensor can measure the temperature of each pixel and assisting in the accurate correction of image sensor in pixel level.
In a digital infrared focal plane array (IRFPA) thermal imager, imaging circuit has requirements of receiving serial data from digital FPA correctly and stably. Conventional data receiving method has disadvantages of low speed, low stability and poor adaptability, which results from clock synchronization difficulty at high data rate and unfixed serial link delay. A novel data receiving method basing on deserializer and sequence detection is proposed. Benefiting from the deserializer, high speed sampling can be implemented, and clock synchronization difficulty is lowered down. With sequence detection, not only the beginning of data packet but also the best sampling point can be correctly determined, even though an uncertain serial link delay exists. The proposed method has been implemented in FPGA achieving a single channel data receiving rate up to 550Mbps. Shaking table testing is completed which fully verifies the high stability and good adaptability of the proposed method.
This paper presents a logarithmic response burst mode IRFPA ROIC with pixel level integration of BDI structure and memory cells. BDI structure provides stable bias for the detector, and converts detector current into logarithmic voltage fast. On-chip high speed video record is achieved by high speed sampling the logarithmic response voltage and storing it into the memory cells in order. A column level SAR ADC is used to convert the outputs of memory cells into digital code. The prototype chip with 64×64 pixels was designed and fabricated. Ultra-high speed video capturing at 1Mfps with 100 consecutive frames is successfully demonstrated.
This paper presents a two-step ADC architecture for dual band infra-red focal plane array (IRFPA). It has advantages of small pixel area and low power over conventional pixel level ADC while maintaining the characteristic of enhancing well capacity of ROIC. The proposed two-step ADC with 16 bits is designed for middle / long wave (MW/LW) dual band IRFPA: 10-bit pulse frequency modulation (PFM) based pixel level ADC with 6-bit column paralleled Successive Approximation Register (SAR) ADC is employed for LW detector and 6-bit PFM based pixel level ADC with 10-bit column paralleled SAR ADC is employed for MW detector. Layout area of the pixel is 30 μm × 30 μm. The simulation result shows the DNL of the proposed two-step ADC for LW detector and MW detector are 0.6 LSB and 0.9 LSB respectively.
Digital infrared (IR) focal plan array (IRFPA) is one of the most significant characteristic of advanced IR imaging systems, it is implemented by integrating ADCs into the readout integrated circuit (ROIC). Successive Approximation Register (SAR) ADC is popular for column-level ADC architecture since it has low power and high resolution. In this paper a 14-bit RC hybrid SAR ADC with unary capacitor array is proposed, it has better linearity performance area compared with conventional SAR ADC. The proposed SAR ADC introduces resistor ladder for the last 6-bit conversion and it is shared by the whole SAR ADC array, so single SAR ADC’s layout’s length can be reduced, The proposed SAR ADC is designed in 130 nm standard CMOS process, the size of the SAR ADC core is 30 μm × 560 μm. the post simulation result show that its power consumption is 102 μW when the sampling rate is 100 kHz, and the worst DNL is 0.4 LSB when mismatching of 0.2% of capacitor array is introduced. The proposed SAR ADC suits for digital IRFPA applications.
Digital readout integrated circuit (ROIC) has become the development tendency of ROIC for infrared focal plane array (IRFPA) due to its advantages such as improved ability of resisting interference, high readout rate and low readout noise. Compared with traditional analog ROIC, column-parallel analog-to-digital converters (ADCs) are integrated on digital ROIC. Because of the non-ideality of CMOS process, the column nonuniformity of digital ROIC is more obvious than that of analog ROIC due to device mismatch, which will lead to obvious column fixed pattern noise (FPN). In order to reduce column nonuniformity, the main sources of column nonuniformity in digital ROIC are analyzed firstly, including the mismatch between column analog readout channels, as well as ADCs. Then, analytical models have been developed to reveal the relationship between the column FPN and design parameters of digital ROIC. And the numerical computation with CMOS process parameters is implemented. The results show that the column FPN caused by digital ROIC can be reduced to less than 0.1% when the transistor area of tail current source in column analog readout channel is larger than 10μm2 and input transistor area of the first operational amplifier in ADC is larger than 20μm2 . By the help of the proposed mismatch model, column FPN of digital ROIC can be reduced over ten times with optimized design parameters, which provides beneficial guidance for digital ROIC design.
KEYWORDS: Synthetic aperture radar, Quantization, High dynamic range imaging, Signal to noise ratio, Readout integrated circuits, Amplifiers, Image sensors, Imaging systems
This paper presents a two-step ADC architecture for high dynamic range, high sensitivity image sensor. The proposed two-step ADC architecture works in two phases: the coarse quantization phase in each pixel, digital integration technique is applied to increase the well capacity as well as system’s dynamic range, and a capacitive transimpedence amplifier (CTIA) scheme is employed to achieve high sensitivity; The fine quantization phase in the column which reduces the bit width of the pixel-level ADC, pixel-level ADC’s noise and layout area are reduced consequently. The proposed two-step ADC with 18 bits is designed in 0.18 μm standard CMOS process. The optimized assignment for the bit width of pixel-level ADC and column paralleled ADC is applied. The simulation shows the signal to noise ratio (SNR) is 93.5 dB. The dynamic range is 108 dB. The least sensible electrons are 781 e-. The simulation results indicate the proposed twostep ADC is suitable for high dynamic range, high sensitivity image sensor.
A high speed and high dynamic range digital ROIC for infrared FPA detectors is proposed. With using pixel-level ADC and parallel high speed transmission technology, frame rate and dynamic range of the digital ROIC is greatly improved. A 384×288 digital ROIC with pixel parallel charge packet counting ADCs and 4 parallel transmission channels is designed and fabricated using 0.11μm CMOS technology to verify the proposed ROIC architecture. With the proposed ROIC, a high speed high dynamic range infrared FPA detector is achieved with a frame rate of up to1000Hz and a dynamic range of up to 85dB.
Ultra-low expansion glass-ceramic is a kind of functional materials, which has been extensively researched and widely used in various aspects because of its high performance. This paper introduces the optical mechanism and research progress of glass-ceramic. Also the application in aerospace area as laser gyro, objects telescope is illustrated. In addition to this, the preparation methods and prospects of ultra-low expansion glass-ceramic is discussed.
A novel data transmission circuit for digital image sensors is presented. Large amounts of data are divided into m groups of n bits each. Each group of data is stored in an n-bit shift register. Under the control of a column scanner, at a time, only one group of data is selected to output serially to a common output line. Thus, as the scanner scans all the groups of data, the large amounts of data are serially output through the common line. A current-mode circuit transforms the output data into a low voltage swing signal which propagates over the common output line fast. A sense amplifier receives the low voltage swing signal and then recovers the full swing signal. Finally, a low-voltage differential signaling ( LVDS ) transmitter, which is fed with the full swing signal, transmits the data out chip. Because there is always only one of the m shift registers operating, the power consumption is greatly reduced. The simulation results show that the proposed circuit works correctly at a date rate of 400Mb/s. For n=14, and m=8, 32, 128, and 256, the power consumption of the prototype is as low as 1/4, 1/15, 1/50, and 1/80 that of the traditional serial link respectively.
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