Mr. Henning Haffner Profile

Henning Haffner

at Intel Corp

SPIE Involvement:

Author

Publications (12)

SPIE Journal Paper | 19 March 2012

Escaping death: single-patterning contact printing for 32/28-nm logic technology nodes

Bradley Morgenfeld, Ian Stobert, Ju Jin An, Massud Aminpur, Colin Brodsky, Alan Thomas, Henning Haffner, Martin Ostermayr, Hideki Kanai, Norman Chen

JM3, Vol. 11, Issue 1, 013010, (March 2012) https://doi.org/10.1117/12.10.1117/1.JMM.11.1.013010

KEYWORDS: SRAF, Printing, Optical proximity correction, Optical lithography, Critical dimension metrology, Etching, Logic, Photomasks, Semiconducting wafers, Model-based design

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Proceedings Article | 4 April 2011 Paper

Single exposure contacts are dead. Long live single exposure contacts!

Henning Haffner, Martin Ostermayr, Hideki Kanai, Chan Sam Chang, Bradley Morgenfeld, Jujin An, Meng Luo, Haoren Zhuang

Proceedings Volume 7974, 79740E (2011) https://doi.org/10.1117/12.879681

KEYWORDS: Optical proximity correction, Etching, Silicon, Double patterning technology, Oxides, Photomasks, Lithography, Logic, Printing, Semiconducting wafers

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Proceedings Article | 23 March 2011 Paper

Applicability of global source mask optimization to 22/20nm node and beyond

Kehan Tian, Moutaz Fakhry, Aasutosh Dave, Alexander Tritchkov, Jaione Tirapu-Azpiroz, Alan Rosenbluth, David Melville, Masaharu Sakamoto, Tadanobu Inoue, Scott Mansfield, Alexander Wei, Young Kim, Bruce Durgan, Kostas Adam, Gabriel Berger, Gandharv Bhatara, Jason Meiring, Henning Haffner, Byung-Sung Kim

Proceedings Volume 7973, 79730C (2011) https://doi.org/10.1117/12.879703

KEYWORDS: Source mask optimization, Photomasks, Resolution enhancement technologies, Optical proximity correction, Tolerancing, Optical lithography, SRAF, Image processing, Lithography, Semiconducting wafers

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Proceedings Article | 1 April 2008 Paper

32 nm logic patterning options with immersion lithography

K. Lai, S. Burns, S. Halle, L. Zhuang, M. Colburn, S. Allen, C. Babcock, Z. Baum, M. Burkhardt, V. Dai, D. Dunn, E. Geiss, H. Haffner, G. Han, P. Lawson, S. Mansfield, J. Meiring, B. Morgenfeld, C. Tabery, Y. Zou, C. Sarma, L. Tsou, W. Yan, H. Zhuang, D. Gil, D. Medeiros

Proceedings Volume 6924, 69243C (2008) https://doi.org/10.1117/12.784107

KEYWORDS: Photomasks, Double patterning technology, Logic, Lithography, Etching, Optical lithography, Optical proximity correction, Immersion lithography, Printing, Image processing

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The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

Proceedings Article | 7 March 2008 Paper

Double exposure double etch for dense SRAM: a designer's dream

Chandra Sarma, Allen Gabor, Scott Halle, Henning Haffner, Klaus Herold, Len Tsou, Helen Wang, Haoren Zhuang

Proceedings Volume 6924, 692429 (2008) https://doi.org/10.1117/12.772985

KEYWORDS: Etching, Optical lithography, Double patterning technology, Tolerancing, Image processing, Photomasks, Lithography, Logic devices, Semiconducting wafers, Oxides

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Proceedings Article | 30 October 2007 Paper

Paving the way to a full chip gate level double patterning application

Henning Haffner, Jason Meiring, Zachary Baum, Scott Halle

Proceedings Volume 6730, 67302C (2007) https://doi.org/10.1117/12.746116

KEYWORDS: Double patterning technology, Photomasks, SRAF, Critical dimension metrology, Optical lithography, Tolerancing, Optical proximity correction, Etching, Printing, Lithography

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Double patterning lithography processes can offer significant yield enhancement for challenging circuit designs. Many decomposition (i.e. the process of dividing the layout design into first and second exposures) techniques are possible, but the focus of this paper is on the use of a secondary "cut" mask to trim away extraneous features left from the first exposure. This approach has the advantage that each exposure only needs to support a subset of critical features (e.g. dense lines with the first exposure, isolated spaces with the second one). The extraneous features ("printing assist features" or PrAFs) are designed to support the process window of critical features much like the role of the subresolution assist features (SRAFs) in conventional processes. However, the printing nature of PrAFs leads to many more design options, and hence a greater process and decomposition parameter exploration space, than are available for SRAFs. A decomposition scheme using PRAFs was developed for a gate level process. A critical driver of the work was to deliver improved across-chip linewidth variation (ACLV) performance versus an optimized single exposure process while providing support for a larger range of critical features. A variety of PRAF techniques were investigated by simulation, with a PrAF scheme similar to standard SRAF rules being chosen as the optimal solution [1]. This paper discusses aspects of the code development for an automated PrAF generation and placement scheme and the subsequent decomposition of a layout into two mask levels. While PrAF placement and decomposition is straightforward for layouts with pitch and orientation restrictions, it becomes rather complex for unrestricted layout styles. Because this higher complexity yields more irregularly shaped PrAFs, mask making becomes another critical driver of the optimum placement and clean-up strategies. Examples are given of how those challenges are met or can be successfully circumvented. During subsequent decomposition of the PrAF-enhanced layout into two independent mask levels, various geometric decomposition parameters have to be considered. As an example, the removal of PrAFs has to be guaranteed by a minimum required overlap of the cut mask opening past any PrAF edge. It is discussed that process assumptions such as CD tolerances and overlay as well as inter-level relationship ground rules need to be considered to successfully optimize the final decomposition scheme. Furthermore, simulation and experimental results regarding not only ACLV but also across-device linewidth variation (ADLV) are analyzed.

Proceedings Article | 26 March 2007 Paper

ACLV driven double-patterning decomposition with extensively added printing assist features (PrAFs)

Jason Meiring, Henning Haffner, Carlos Fonseca, Scott Halle, Scott Mansfield

Proceedings Volume 6520, 65201U (2007) https://doi.org/10.1117/12.712558

KEYWORDS: SRAF, Printing, Photomasks, Etching, Lithography, Optical lithography, Optical proximity correction, Critical dimension metrology, Double patterning technology, 3D modeling

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Proceedings Article | 20 October 2006 Paper

Mastering double exposure process window aware OPC by means of virtual targets

Henning Haffner, Zachary Baum, Carlos Fonseca, Scott Halle, Lars Liebmann, Arpan Mahorowala

Proceedings Volume 6349, 63491W (2006) https://doi.org/10.1117/12.687609

KEYWORDS: Optical proximity correction, Photomasks, Model-based design, Logic, Process modeling, SRAF, Critical dimension metrology, Photoresist processing, Tolerancing, Image processing

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Proceedings Article | 10 July 2003 Paper

Improved manufacturability by OPC based on defocus data

Jorg Thiele, Ines Anke, Henning Haffner, Armin Semmler

Proceedings Volume 5042, (2003) https://doi.org/10.1117/12.485251

KEYWORDS: Optical proximity correction, Critical dimension metrology, Photomasks, Semiconducting wafers, Manufacturing, Tolerancing, Lithography, Silicon, Image transmission, Scanning electron microscopy

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Proceedings Article | 2 June 2003 Paper

Aerial image-based mask inspection: a development effort to detect what might impact printing image quality on wafers

Roman Liebe, Henning Haffner, Shirley Hemar, Anja Rosenbusch, Jerry Chen, Franklin Kalk

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483535

KEYWORDS: Inspection, Photomasks, Semiconducting wafers, Reticles, Optical proximity correction, Image quality, Printing, Image enhancement, Detector development, Optical lithography

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Proceedings Article | 27 December 2002 Paper

Automated flow for site definition and CD measurement with a SEM for use in mask production

Christian Rotsch, Henning Haffner, Christian Ruebekohl, Bettine Buechner

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.468082

KEYWORDS: Reticles, Photomasks, Scanning electron microscopy, Computed tomography, Critical dimension metrology, Pattern recognition, Image registration, Metrology, Visualization, Algorithm development

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Proceedings Article | 5 September 2001 Paper

Defect printability study with programmed defects on halftone reticles

Wolfgang Dettmann, Henning Haffner, Jan Heumann, Roman Liebe, R. Ludwig, R. Moses

Proceedings Volume 4409, (2001) https://doi.org/10.1117/12.438398

KEYWORDS: Photomasks, Scanning electron microscopy, Halftones, Semiconducting wafers, Printing, Inspection, Reticles, Image transmission, Phase shifts, Wafer-level optics

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Showing 5 of 12 publications

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