Proceedings Article | 12 October 2021
Kenji Yamamoto, Hideyuki Wada, Yoshio Suzaki, Kazuhiro Sato, Satoshi Iino, Satoru Jimbo, Osamu Morimoto, Mitsuru Hiura, Nilabh Roy, Anshuman Cherala, Jin Choi
KEYWORDS: Distortion, Photomasks, Nanoimprint lithography, Semiconducting wafers, Overlay metrology
Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field/shot-by-field/shot deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity.
Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay, defectivity and throughput.
Advanced memories, such as DRAM and phase change memory are challenging, because the roadmap for these devices calls for continued scaling, eventually reaching half pitches of 14nm and beyond. Scaling also impacts the overlay budget. For DRAM, as an example, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1nm - 2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). This makes a direct printing process, such as NIL an attractive solution.
In previous papers, overlay has been addressed by applying methods that are unique to NIL. In 2018, Hiura et al. reported a mix and match overlay (MMO) of 3.4 nm and a single machine overlay (SMO) across the wafer was 2.5nm using an FPA-1200 NZ2C four station cluster tool. These results were achieved by combining a magnification actuator system with a High Order Distortion Correction (HODC) system, thereby enabling correction of high order distortion terms up to K30. The HODC system utilizes a digital micro mirror array to correct distortion on a field-by-field basis. Further improvements to the system have been achieved by extending the range of the HODC system by applying a diamond like carbon film to the wafer chuck in order to reduce friction. Other process variables that are unique to NIL and that can be considered as process tunable variables include imprint force and tip/tilt of the imprint head relative to the wafer substrate during exposure. These variables can be used to modulate and control the overlay errors near the imprint field edges and provide good overlay control.
An additional method to improve overlay is Drop Pattern Compensation (DPC). DPC is used to create a resist drop pattern designed to remove non-flatness originating either from the wafer/wafer chuck or pattern topography, so as to minimize mask bending. Finally, it is also possible to correct distortion signatures on wafer by fabricating a “refined” mask which takes into account the distortion signature. The purpose of this paper is to describe the application of the improvements discussed above to realize a mix and match overlay of less than 3nm.
