The paper examines the viability of various levelling options1 on Nikon i11, i12 and i14 steppers in compensating for across field differences in focus position. The analysis was performed on both production wafers at various processing stages and test wafers with oxide deposited then etched to different depths. The main analysis technique used was the stepper focus measurement system along with Hitachi 9220 CDSEM measurements and levelling beam analysis using a CCD camera2. The conclusion from the paper is that due to diffraction effects of the levelling beam, levelling-on can introduce large wafer stage tilts and so reduce CD control in the i11's and i12's. Since the EGL method also uses the levelling sensor in conjunction with the focus sensors this also introduces large tilts causing large across field CD variation.
Modern photolithography uses wafer steppers to project the image of a given circuit layer from a reticle onto a photoresist-covered wafer. In the sub-wavelength exposure regime (where the imaging wavelength is greater than the feature being imaged) the wafer surface needs to be positioned within a few hundred nanometers of the stepper focal plane to maintain imaging fidelity. Since typical wafer surface flatness variation is far in excess of this, imaging is accomplished by continuously focussing on the wafer surface during the exposure operation. For 'edge shots', where the centre of the stepper field gets close to the wafer edge, the focussing challenge gets very severe due to increasing wafer flatness variation. The focussing position is determined from the top surface of the resist. However at the edge of the wafer the resist thickness is not uniform, due to effects of the wafer edge bead. This leads to errors in the correct focus offset value been picked to place the wafer surface position within a few hundred nanometers of the stepper focus plane. These variations have a direct impact on yield, especially in sub- wavelength processes, and effects a sizeable proportion of the wafer surface area. This paper describes the yield improvement activities under taken on an i-line 0.35um BiCMOS process. This work comprises of three main parts. The first area investigated, was the changing resist thickness profile at the edge of the wafer.
Contrast Enhancement Lithography has been in existence for almost two decades, yet its practical advantages are relatively unknown among the general lithography community. This paper attempts to redress this situation by discussing the implementation of a Contrast Enhancement Material into manufacturing. Contrast Enhancement Materials (CEMs) are photobleachable solutions applied as a thin top coat to the photoresist after softbake. The CEM is initially opaque at the actinic wavelength but becomes essentially transparent upon exposure. Optimising the relative bleaching parameters of the photoresist and the Contrast Enhancement Material makes it possible to prevent exposure in nominally unexposed resist regions, while bleaching the exposed resist areas. Thus, a temporary contact mask is formed on the photoresist during exposure, allowing high-intensity parts of the aerial image to pass through while eliminating low intensity regions. The resulting aerial image which exposes the photoresist has higher contrast than the original. This allows superior resist depth-of-focus, improves resist profile, increases exposure latitudes and reduces proximity effects among other benefits. Initially, this paper discusses the chemistry and physics of the CEM process. Next the authors look at the lithographic requirements for a final metal level on a sub-micron CMOS process. Analysis of the Depth-Of-Focus error budget indicated that the process would not be manufacturable without significantly increased DOF. The authors also present the results of the characterization of the CEM, including simulation work, with regard to the effect on primary lithography outputs such as depth-of-focus, resist sidewall and exposure latitude.
Stepper autofocus systems can involve reflecting a light beam off the top surface of the wafer (i.e. the top of the photoresist). The density of underlying circuitry causes this relative position to vary, and this will then cause focus errors comparable to the step-height of the underlying pattern. The typical depth of focus in sub-micron lithography is of the same order of magnitude as the maximum step-height on the wafer surface due to topography, so these effects have become significant. Therefore, the optimum focus offset may need to be experimentally determined for each product. For a fab which deals with many products (e.g. a foundry) this requires significant amounts of work. This paper investigates the pattern density effect for metal layers and considers the influence of layer thickness, and the planarization properties of the intermetal dielectric on the optimum focus offset. The possible method for calculating the optimum focus offset by taking the average pattern density under the area of the focus beam from a CAD layout is presented. The usefulness of techniques such as Multi-Point Autofocus is also discussed. Finally, the side-benefits of CMP in reducing this effect are quantified.
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