Scaled technology node, SRAMs suffer from increased Bit Line (BL) and Word Line (WL) resistance. To solve these issues, we present SRAM bit-level BL and WL metallization and options suitable for both SADP an EUV. We also present Buried power Rail (BPR) SRAM as enablers for high density SRAM cells (HD-111) in scaled technology nodes for 5nm and beyond and illustrate system level advantages of BPR SRAM with BPR based power delivery network of a hard macro like Arm 64-bit CPU.
Standard cell track height scaling provides us with sufficient area scaling at the standard cell library level. The efficiency of this technique and the complexities involved with this scaling method have been discussed in detail [1,2]. However, the area benefits of standard cell track height scaling diminish when we consider the complexities of incorporating on-chip power grid into the DTCO exploration loop. We have previously outlined several layout techniques to improve the utilization density of this scaling technology [2,4]. However, the proposed techniques only minimize the impact of the power grid on the design. In this work, we discuss the need to combine 3D – μTSV technology and logic technology to decouple the power grid from the design budget. The proposed technique delivers power from the backside of a thinned device wafer using the process steps depicted in Figure 4. Our analysis demonstrates significant area savings and IR-drop reduction. We use SPICE simulations to extract grid resistances as part of our technology targeting process, based upon a high-level on-chip PDN model. We also verify our findings using a commercially available EDA toolchain.
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