A generalized edge-placement yield model for the cut-hole patterning process is developed. It incorporates the cut-hole
overlay errors, cut-hole and grating line/space CD variations into a unified physical model to investigate the key
parameters that affect the edge-placement yield. The yield related features are identified first and probability-of-failure
(POF) functions are introduced to construct the yield formula. The variable number in the yield integral is reduced from
four to two by a special transformation method. Our calculation results show that the cut-hole overhang and (grating)
line/space CD must be optimized in order to achieve the maximum yield. The sensitivity of edge-placement yield to
various statistical parameters is investigated and the overlay errors are found to play a dominant role. We also study the
scaling trend of the edge-placement yield and show that non-trivial challenges of manufacturing (half-pitch) 7-nm
FinFET devices will require significantly improved overlay accuracy and process control.
Self-aligned multiple patterning (SAMP) techniques can potentially scale integrated circuits down to half-pitch 7nm. In this paper, we present a comparative analysis of self-aligned quadruple (SAQP) and sextuple (SASP) techniques by investigating their technological merits and limitations, process complexity and cost structures, strategy of layout decomposition/synthesis, and yield impacts. It is shown that SASP process complexity is comparable to that of SAQP process, while it offers 50% gain in feature density and may be extended for one more node. The overlay yield of cut process is identified to be a challenge when the minimum device feature is scaled to half-pitch 7nm. The mask design issues for various applications using each technique are discussed, and the corresponding layout decomposition/synthesis strategy for complex 2D patterning is proposed. Although the high-dose EUV single-cut process can save significant costs when applied to replace the 193i multiple-cut process to form fin/gate structures, our cost modeling results show that SADP+EUV approach is still not cost effective for patterning other critical layers that generally require the same mask number (and lithographic steps) as the non-EUV schemes.
In this paper, we present a cut-process overlay yield model for self-aligned multiple patterning and study how its yield will be affected by the overlay errors and cut-hole overhang. A geometric model is developed to identify the yield-related structures and construct the probability-of-failure (POF) functions. A general formula to calculate the cut-process overlay yield is derived using the joint POF function. Our calculation results show that an optimal cut-hole overhang must be found in order to achieve the maximum yield. The scaling tendency of the cut-process overlay yield is also studied, and it is found to be a potential challenge when the half pitch of device features reaches 7nm. The yields of 4-mask 193i and single-mask EUV cut modules are also calculated for a comparison. Moreover, a post-lithography misalignment correction technique based on dry etching is proposed. A geometric tilted etching model is developed to predict the relation between the tilting angle of an etching process and the shifted distance of the etched structure’s mass center.
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