A multi-objective optimization flow is developed to identify balanced compact optical proximity correction (OPC) models with ideal calibration accuracy, runtime performance and prediction accuracy. We demonstrate a model selection process based on Pareto front optimization to meet multiple modeling requirements in a single optimization step. A genetic search algorithm determines the final population that offers the best trade-off in set model properties. As a demonstration, we cooptimize calibration accuracy, verification accuracy and term count in a mode developed for hot spot prediction for a line and space memory layer. The optimization determines the minimum number of model terms to meet the off-nominal dose and focus patterning accuracy requirements in verification. Multi-objective optimization provides better verification process window condition (PWC) accuracy because of the multi-objective trade-off built into the genetic algorithm (GA). The optimizer also provides better calibration accuracy (Rms Weighted) than compact models with a fixed configuration because model composition is optimized during GA search. The resulting champion model is 30% more predictive and 5% faster in simulation using this approach. Results for a negative tone develop hole layer with a model complexity of up to 44 terms are also analyzed based on nominal only measurement data. We further show the models selected by multi-objective optimization have a lesser tendency to over-fit the calibration data. The methodology can be applied to streamline complex models for optimum performance and target error rate. In many cases, for smaller data sets, we show that simplified models provide improved verification accuracy within metrology error limits.
We introduce a new algorithm (DFM Via Shift) to reposition vertical interconnect access (VIA) design patterns, considering the retargeted metal (both upper and lower layer) pattern, the user-defined max-shifting range, and the VIA design rule, for the purpose of achieving maximum metal coverage of VIAs. The DFM Via Shift algorithm considers VIAs that interact with each other based on spacing rules as a VIA cluster. All VIAs in a cluster are co-optimized, allowing for fully-covered VIAs with good positioning to be shifted to allow other, more critical VIAs to be optimized in some scenarios. We present the results of our research showing that the overall metal coverage of VIAs in 25nm node test chips can be significantly improved with repositioning. Nearly 95% of VIAs exposed out of metal after retargeting can be optimized to new, fully-covered positions in one of the test cases of the advanced node.
KEYWORDS: Design for manufacturing, Databases, Rule based systems, Semiconducting wafers, System identification, Visualization, Photomasks, Lutetium, Microelectronics, Design for manufacturability
In this paper we combined the hotspot pattern library and the rule-based scoring system into a modularized hotspot-checking rule deck running on an automatic flow. Several DFM (design for manufacture) properties criteria will be defined to build a “score board” for hotspot candidates. When hotspots in the input design are highlighted, the scoring system can identify whether a hotspot is a high risk hotspot or not, and define the severity of the hotspots by extracted DFM properties. The automatic flow will detect which layers are contained in the design then generate a modular rule deck with several corresponding hotspot check modules. The flow also takes snapshots of the high risk hotspots according to the score board automatically. After all the essential hotspot data is collected, the flow will automatically create an HTML-format report which has histograms of properties and overview graph that shows the distribution of hotspots. The aforementioned HTML report containing scored DFM properties and snapshots can help result-viewers to identify the high risk hotspots on the design quickly; namely, users can examine hotspots by snapshots without loading the whole design into layout viewer tools. By comparing the hotspot checking result with real defects from wafer data, a true hotspot’s values of DFM properties can be obtained. We believe this is helpful for users to improve their hotspot rules in accuracy.
The Mask Data Correctness Check (MDCC) is a reticle-level, multi-layer DRC-like check evolved from mask rule
check (MRC). The MDCC uses extended job deck (EJB) to achieve mask composition and to perform a detailed check
for positioning and integrity of each component of the reticle. Different design patterns on the mask will be mapped to
different layers. Therefore, users may be able to review the whole reticle and check the interactions between different
designs before the final mask pattern file is available. However, many types of MDCC check results, such as errors from
overlapping patterns usually have very large and complex-shaped highlighted areas covering the boundary of the design.
Users have to load the result OASIS file and overlap it to the original database that was assembled in MDCC process on
a layout viewer, then search for the details of the check results. We introduce a quick result-reviewing method based on
an html format report generated by Calibre® RVE. In the report generation process, we analyze and extract the essential
part of result OASIS file to a result database (RDB) file by standard verification rule format (SVRF) commands.
Calibre® RVE automatically loads the assembled reticle pattern and generates screen shots of these check results. All the
processes are automatically triggered just after the MDCC process finishes. Users just have to open the html report to
get the information they need: for example, check summary, captured images of results and their coordinates.
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