With the adoption of extreme ultraviolet (EUV) lithography for high-volume production of advanced nodes, stochastic variability and resulting failures, both post litho and post etch, have drawn increasing attention. There is a strong need for accurate models for stochastic edge placement error (SEPE) with a direct link to the induced stochastic failure probability (FP). Additionally, to prevent stochastic failure from occurring on wafers, a holistic stochastic-aware computational lithography suite of products is needed, such as stochastic-aware mask source optimization (SMO), stochastic-aware optical proximity correction (OPC), stochastic-aware lithography manufacturability check (LMC), and stochastic-aware process optimization and characterization. In this paper, we will present a framework to model both SEPE and FP. This approach allows us to study the correlation between SEPE and FP systematically and paves the way to directly correlate SEPE and FP. Additionally, this paper will demonstrate that such a stochastic model can be used to optimize source and mask to significantly reduce SEPE, minimize FP, and improve stochastic-aware process window. The paper will also propose a flow to integrate the stochastic model in OPC to enhance the stochastic-aware process window and EUV manufacturability.
Despite being crucial in an optical lithography process, “dose” has remained a relative concept in the computational lithography regime. It usually takes the form of a percentage deviation from a pre-identified “nominal condition” under the same illumination shape. Dose comparison between different illumination shapes has never been rigorously defined and modeled in numerical simulation to date. On the other hand, the exposure-limited nature of EUV lithography throughput demands the * illumination shape being optimized with the physical dose impact consciously taken into consideration. When the projection pupil is significantly obscured (as in the ASML EXE high NA scanner series), the lack of a proper physical dose constraint may lead to suboptimal energy utilization during exposure. In this paper, we demonstrate a method to accurately model the physical dose in an optical lithography process. The resultant dose concept remains meaningful in the context of a changing illumination pupil, which enables co-optimization of imaging quality and a throughput metric during the Source-Mask Optimization (SMO) phase, known as the Dose-Aware SMO. With a few realistic test cases we demonstrate the capability of Dose-Aware SMO in terms of improving EUV throughput via reducing the effective exposure time, in both regular and obscured projection systems. The physical dose modeling capability in computational lithography not only addresses those immediate challenges emergent from EUV throughput, but also opens the gate towards a broad class of exciting topics that are built upon physical dose, such as optical stochastic phenomena and so on.
All chipmakers understand that variability is the adversary of any process and reduction is essential to improving yield which translates to profit. Aggressive process window and yield specifications necessitate tight inline variation requirements on the DUV light source which impact scanner imaging performance. Improvements in reducing bandwidth variation have been realized with DynaPulse™ bandwidth control technology as significant reduction in bandwidth variation translates to a reduction in CD variation for critical device structures.
Previous work on a NAND Via layer has demonstrated an improvement in process capability through improve source and mask optimization with greater ILS and reduced MEEF that improved CDU by 25%. Using this Via layer, we have developed a methodology to quantify the contribution in an overall CDU budget breakdown. Data from the light source is collected using SmartPulse™ allowing for the development of additional methodologies using predictive models to quantify CD variation from Cymer’s legacy, DynaPulse 1 and DynaPulse 2 bandwidth control technologies. CD non-uniformities due to laser bandwidth variation for lot to lot, wafer to wafer, field to field and within field is now available based on known sensitivities and modeled. This data can assist in understanding the contribution from laser bandwidth variation in global and local CDU budgets.
Inverse lithography is increasingly being used as a viable OPC solution to maximize process window (PW), improve CD uniformity (CDU) and minimize the mask error factor (MEF), especially for memory devices. The device yield is typically limited by the process window of a few critical layers, and the Via layer is identified as one of the process window limiters for advanced 3D-NAND devices. To maximize the on-chip yield, ASML has developed advanced image based Mask-3D (M3D) inverse technology that can optimize freeform mask shapes and enhance design printability throughout the mask optimization flow. Mask rule checks (MRC) and side-lobe printing are optimized simultaneously to deliver the maximum process window.
The advanced image based M3D inverse lithography technology (ILT) is used to perform full chip mask correction on the Via layer of a 3D-NAND device. 3D NAND devices contain highly repetitive cell and page buffer patterns. To ensure the full chip device performance, the consistency of the mask correction is important. Our strategy is to use the computationally intensive mask optimization solution from the new advanced image based M3D inverse technology to generate a freeform mask which gives the best lithography performance. We then use Tachyon’s Pattern Recognition and Optimization (PRO) engine to propagate the freeform mask solution of the repetitive patterns to the full chip. The periphery of the chip is optimized using conventional OPC methods. The simulation results from the advanced image based M3D inverse technology are compared against the baseline flow, which uses a standard inverse solution. The simulation results from both the flows are further validated on wafer. Significant improvement in overlapping process window (OPW) and CD uniformity is observed using the new advanced inverse technology. The simulation data shows a 32% improvement in depth of focus (DOF), a 5% improvement in the image log slope (ILS) and a 25% reduction in best focus shift (BFS) range. The improvement has also been verified at the wafer-level.
Shrinking pattern sizes dictate that scanner-to-scanner variations for HVM products shrink proportionally. This paper shows the ability to identify (a subset of) root causes for mismatch between ArF immersion scanners using scanner metrology. The root cause identification was done in a Samsung HVM factory using a methodology (Proximity Matching Budget Breakdown or PromaBB) developed by ASML. The proper identification of root causes-1 helps to select what combination of scanner control parameters should be used to reduce proximity differences of critical patterns while minimizing undesirable side effects from cross-compensation. Using PromaBB, the difference between predicted and measured CD mismatch was below 0.2nm. PromaBB has been proposed for HVM implementation at Samsung in combination with other ASML fab applications: Pattern Matcher Full Chip (PMFC), Image Tuner and FlexWave.
Semiconductor nanowire (NW) solar cells have promising potentials in solar energy conversion, benefiting from
their low fabrication cost and enhanced optical absorption through light confinement. Recently, we have shown that the
absorption efficiency can be significantly improved in lead sulfide (PbS) NWs with high refractive indices, by a direct
observation of 350% external quantum efficiency (EQE). In this proceeding paper, we further examine the optical
resonance mechanism in this promising nanomaterial. Particularly, we will present our recent results on resonance
modes calculation, polarization and substrate effects on optical resonance, and intensity dependent minority carrier
diffusion lengths in single PbS NW Schottky junction solar cells.
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