As wafer manufacturing shrinks size and pitch of features, and EUV lithography introduces high NA, the control of photomask pattern placement error that contributes to wafer overlay becomes a critical requirement for leading-edge devices. For sub-3nm node devices, the pattern complexity has increased and the exposure dose has also risen due to the use of low-sensitivity resist. Accordingly, to improve the pattern fidelity and reduce the exposure time, masks are manufactured using Multi-Beam Mask Writer (MBMW). As a result of analyzing the mask pattern placement error budget for the main EUV resist of sub-3nm node device, e-beam resist charging was found to be the most significant factor. This is primarily due to the inability to use a charging dissipation layer (CDL), caused by defect issues and degradation of critical dimension (CD) linearity. In this paper, we conduct an in-depth analysis of mask pattern placement errors induced by the charging effect in the MBMW and present a charging control methodology to mitigate these pattern-density-dependent errors. We test the charging effect reduction, an integrated solution of hardware and software for charging control in the MBMW, and showcase its performance for two resists. When applied to mass productions, the charging effect correction (CEC) significantly reduces mask pattern placement errors in a single cell and improves mask overlay between two critical layers aligned in an overlay alignment scheme. Ultimately, this leads to a reduction of wafer in-field overlay error.
The wafer manufacturing industry has increased pattern complexity of the main feature and sub-resolution assist feature (SRAF) required for improving the EUV lithography process window and enabling the leading-edge technology nodes. In parallel, Inverse Lithography Technology (ILT) and its requirements of curvilinear data structure has gained momentum in recent years, putting the pressure on mask makers, in particular the mask writer. To fulfill the curvilinear feature requirements of high pattern resolution and large data volume, the mask writer needs to develop innovative techniques and update its error compensation strategies. In this paper, we will investigate the pattern resolution, local critical dimension uniformity (LCDU), and line edge roughness (LER) and explore the projected improvements in multi-beam writer technology and highlight its capability against EUV lithography requirements. We will also investigate the role of resist and process on these critical mask metrics to illustrate the overall performance against wafer requirements.
EUV mask exposure tests were conducted at Intel Mask Operation (IMO) on a MBMW201 multi-beam writer to study the effects of writing beam diameter and associate blurs, mask exposure dose, and photoresist on pattern resolution, LCDU, and LER. An analytical model was also used to predict the trend and determine the dependency of these lithographic metrics on the writer exposure conditions.
Multibeam mask writers (MBMW) from IMS Nanofabrication developed in the last decade are currently being used for leading edge mask patterning. The ability to utilize low sensitivity resists required to pattern complex mask patterns with good edge placement control made MBMW the tool of choice for leading edge extreme ultraviolet (EUV) mask patterning. The next generation of High-NA EUV masks will require smaller features, more complex figures and reduction of edge placement errors. These requirements may exceed the capability of the current MBMW tools. Recently IMS announced the next generation MBMW tools to address this challenge. This paper will explore the effectiveness of the proposed improvements on addressing High-NA EUV mask patterning challenges.
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