Making a sub-100 nm contact hole pattern is one of the difficult issues in semiconductor process. Compared with
another fabrication process, resist reflow process is a good method to obtain very high resolution contact hole. However
it is not easy to predict the actual reflow result by simulation because very complex physics and/or chemistry are
involved in resist reflow process. We must know accurate physical and chemical constant values and many fabrication
variables for better prediction. We made resist reflow simulation tool to predict approximate resist reflow as functions of
pitch, temperature, time, array, and so on. We were able to see the simulated top view, side view and the changed hole
size. We used Navier-Stokes equation for resist reflow. We had varied the reflow time, temperature, surface tension, and
3-dimensional volume effect for old model. However the photoresist adhesion is another very important factor that was
not included in the old model. So the adhesion effect was added on Navier-Stokes equation and found that there was a
distinctive difference in reflowed resist profile and the contact hole width compared to the case of no adhesion effect.
Resist reflow is a simple and cost effective technique by which the resist is baked above the glass transition temperature (Tg) after the typical contact hole pattern has been exposed, baked and developed. Resist reflow method can obtain very high resolution without the loss of process margin than any other resolution enhancement techniques that can make the same linewidth. But it is difficult to predict the results of the thermal flow and the process optimization. If the results of reflow process can be exactly predicted, we can save great time and cost. In order to optimize the layout design and process parameters, we develop the resist flow model which can predict the resist reflow tendency as a function of the contact hole size, initial shape and reflow temperature for the normal and elongated contact hole. The basic fluid equation is used to express the flow of resist and the variation of viscosity and density as a function of reflow temperature and time are considered. Moreover surface tension and gravity effects are also considered. In order to build a basic algorism, we assume that the fluid is incompressible, irrotational and Newtonian. First, we consider the boundary movement of side wall and we think the basic equations for free surface flow of fluid as 2-dimensional time-dependent Navier-Stokes equations with the mass conservation equation. Surface tension acting on the interface pressure difference and gravity force that enable the resist flow are also included.
The minimum feature size of the semiconductor device will be smaller and smaller because of the increasing demand for the high integration of the device. According to recently proposed roadmap, ArF immersion lithography will be used for 65 nm to 45 nm technology nodes. Polarization effect becomes a more important factor due to the increasing demand for high NA optical system and the use of immersion lithography. It is important to know that the polarization effect is induced by mask in small size patterning. The unpolarized plane waves leaving the illumination system are diffracted by the mask. So the light beam going through the mask will experience induced polarization by the mask. In this paper, we considered the change of polarization state as a function of mask properties. We calculated vector diffraction of 193 nm incident light. The masks considered are the chromeless mask, a binary chrome mask and 6 % attenuated phase shifting mask. We use the finite-difference time-domain method to solve the Maxwell equation. The aerial image depends on the polarization states induced by the mask properties such as materials, thickness, and pitch.
Resolution enhancement technology (RET) refer to techniques that extend the usable resolution of an imaging system without decreasing the wavelength of light or increasing the numerical aperture (NA) of the imaging tool. Off-axis illumination (OAI) and phase shift mask (PSM) are essentially accompanied with optical proximity correction (OPC) for most devices nowadays. In general, these three techniques do not work in isolation and the most aggressive mainstream lithography approaches use combinations of all RETs. In fact, OAI and PSM are essentially useless for typical chip-manufacturing applications unless accompanied by OPC. For low k1 imaging, strong OAI such as Quasar or dipole illumination types is the best. We used dipole illumination in this study. By using strong OAI, the amplitude of the 0th order is decreased and the amplitude of the 1st order is increased. Chromeless phase lithography (CPL) is one of PSM technologies and CPL mask is the possible solution for small geometry with low mask error enhancement factor (MEEF). CPL uses only 180 degrees phase-shifter on transparent glass without chromium film to define light-shielding region, destructive interference between light transmitted through the 0 degree and 180 degrees regions produces dark images. To obtain the best resolution, proper OPC is required with CPL. While the most common and straightforward application of OPC is to simply move absorber edges on the mask by giving simple mask bias, the interesting and important additional technique is the use of scattering bars. Also, we can use zebra patterns for the transmission control. Mask intensity transmission changes can impact the image quality. Zebra patterns are formed by adding chromium transverse features. The transmission will be controlled by the zebra pattern density. Technology node with ArF source is studied and the mask optimization is found to be a critical. And the linewidth of scattering bars, transmission (using zebra feature) are varied at line and space (L/S) patterns. We used 65 nm node 5 L/S and 45 nm node isolated line pattern. In order to optimize the zebra pattern density, we need to control the line width and pitch of the zebra patterns. For dense line and isolated line, the use of scattering bars and zebra patterns affected target critical dimension. We found out the better process window at dense 65 nm node by comparing the use of scattering bars with zebra patterns. Likewise, we optimized the isolated 45 nm node.
MEEF (Mask Error Enhancement Factor) is the most representative index which CD (Critical Dimension) variation in wafer is amplified by real specific mask CD variation. Already, as it was announced through other papers, MEEF is increased by small k1 or pattern pitch. Illumination system, just like lens aberration or stage defocus affects directly MEEF value, but the leveling or species of substrate and the resist performance are also deeply related to MEEF value. Actually, when the engineers set up the photo process of shrink structure in current device makers, they established minimum shot uniformity target such as MEEF value within wafer uniformity and wafer to wafer uniformity, besides UDOF (Usable Depth of Focus) or EL (Exposure Latitude) margin.
We examined MEEF reduction by checking the difference in resist parameters and tried to correlate the results between experiment and simulation. Solid-C was used for simulation tool. The target node was dense L/S (Line/Space) of sub-80 nm and we fix the same illumination conditions. We calculated MEEF values by comparing to original mask uniformity through the optical parameters of each resist type. NILS (Normalized Image Log Slope) shows us some points of the saturation value with pupil mesh points and the aberration was not considered. We used four different type resists and changed resist optical properties (i.e. n, k refractive index; A, B, and C Dill exposure parameters). It was very difficult to measure the kinetic phenomenon, so we choose Fickian model in PEB (Post Exposure Bake) and Weiss model in development. In this paper, we tried to suggest another direction of photoresist improvement by comparing the resist parameters to MEEF value of different pitches.
The most important issue in lithography as a semiconductor process is to obtain the minimum resolution. In order to obtain the minimum resolution with processible depth of focus, the numerical aperture is gradually increased and the exposure wavelength is also decreased. The effect of aberration is also increased as a result. It was not much needed to consider the aberration effects for the critical dimensions (CD) greater than around 300 nm. However, it is greatly necessary to consider the effect of aberration for CDs smaller than 100 nm in order to obtain the best process condition. The purpose of this study is to evaluate the aberration effect of the projection system for the specified node and shape of pattern. Evaluation is made by comparing the various aberration effects for the different exposure wavelengths, different shapes such as isolated, line and space, contact hole and L-shaped patterns, and also for the duty ratio by using commercial lithography simulator, SOLID-C [1].
MEEF (Mask Error Enhancement Factor) is the most representative index which CD (Critical Dimension) variation in wafer is amplified by real specific mask CD variation. Already, as it was announced through other papers, MEEF is increased by small k1 or pattern pitch. Illumination system, just like lens aberration or stage defocus affects directly MEEF value, but the leveling or species of substrate and the resist performance are also deeply related to MEEF value. Actually, when the engineers set up the photo process of shrink structure in current device makers, they established minimum shot uniformity target such as MEEF value within wafer uniformity and wafer to wafer uniformity, besides UDOF (Usable Depth of Focus) or EL (Exposure Latitude) margin. We examined MEEF reduction by checking the difference in resist parameters and tried to correlate the results between experiment and simulation. Solid-C was used for simulation tool. The target node was dense L/S (Line/Space) of sub-80 nm and we fix the same illumination conditions. We calculated MEEF values by comparing to original mask uniformity through the optical parameters of each resist type. NILS (Normalized Image Log Slope) shows us some points of the saturation value with pupil mesh points and the aberration was not considered. We used four different type resists and changed resist optical properties (i.e. n, k refractive index; A, B, and C Dill exposure parameters). It was very difficult to measure the kinetic phenomenon, so we choose Fickian model in PEB (Post Exposure Bake) and Weiss model in development. In this paper, we tried to suggest another direction of photoresist improvement by comparing the resist parameters to MEEF value of different pitches.
A full lithography simulation has become an essential factor for semiconductor manufacturing. We have been researching all kinds of problems for lithography process by creating and using our own simulation tool, which has contributed to extracting parameters related to exposure, post exposure bake, and development. Also, its performance has been proved in comparison with other simulation tools. In this paper, our lithography simulator and some of its features are introduced. For its benchmark, we describe our own simulator’s performance and accuracy for whole resist process by the comparison of a commercial tool. The sensitivity of process parameters and process latitude due to its parameters are discussed.
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