Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Computational technologies are still in the course of development for NIL. Only a few simulators are applicable to the nanoimprint process, and these simulators are desired by device manufacturers as part of their daily toolbox. The most challenging issue in NIL process simulation is the scale difference of each component of the system. The template pattern depth and the residual resist film thickness are generally of the order of a few tens of nanometers, while the process needs to work over the entire shot size, which is typically of the order of 10 mm square. This amounts to a scale difference of the order of 106. Therefore, in order to calculate the nanoimprint process with conventional fluid structure interaction (FSI) simulators, an enormous number of meshes is required, which results in computation times that are unacceptable. In this paper, we introduce a new process simulator which directly inputs the process parameters, simulates the whole imprinting process, and evaluates the quality of the resulting resist film. To overcome the scale differences, our simulator utilizes analytically integrated expressions which reduce the dimensions of the calculation region. In addition, the simulator can independently consider the positions of the droplets and calculate the droplet coalescence, thereby predicting the distribution of the non-fill areas which originate from the trapped gas between the droplets. The simulator has been applied to the actual NIL system and some examples of its applications are presented in this work.
Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. All lithographic approaches must establish an ecosystem in order to meet the stringent demands for device manufacturing. The table below shows the performance requirements for each category. Throughput is a basic requirement for cost of ownership. Defectivity addresses device yield. Overlay is also needed to enhance device yield. Each device generation places stricter demands on the overlay budget. An infrastructure is required in order to successfully yield advanced devices. In addition, today’s solutions require computational methods and machine learning to meet the requirements described above. The purpose of this paper is to describe the NIL integration requirements, review some of the key solutions for total integration.
Nanoimprint Lithography (NIL) has been shown to be an effective technique for replication of nano-scale features. The NIL process involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for high volume semiconductor manufacturing. Included on the list are overlay, throughput and defectivity. Imprint lithography, like any lithographic approach requires that defect mechanisms be identified and eliminated in order to consistently yield a device. NIL has defect mechanisms unique to the technology, and they include liquid phase defects, solid phase defects and particle related defects. Especially more troublesome are hard particles on either the mask or wafer surface. Hard particles run the chance of creating a permanent defect in the mask, which cannot be corrected through a mask cleaning process. If Cost of Ownership (CoO) requirements are to be met, it is critical to minimize particle formation and extend mask life. In this work, methods including in-situ particle removal, mask neutralization and resist filtration are discussed in detail. As a result of these methods, along with already developed techniques, particle counts on a wafer were reduced to only 0.0005 pieces per wafer path or a single particle over 2000 wafers, with a next target of 0.0001 pieces per wafer path. Particle adder reduction correlates directly with mask life, and a mask life of 81 lots (about 2000 wafers) is demonstrated. New methods are now under development to further extend mask and reduce cost of ownership. In this work on-tool wafer inspection and mask cleaning methods are also introduced.
Nanoimprint Lithography (NIL) has been shown to be an effective technique for replication of nano-scale features.
Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist
deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows
into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV
radiation, and then the mask is removed, leaving a patterned resist on the substrate.
There are many criteria that determine whether a particular technology is ready for high volume semiconductor
manufacturing. Included on the list are overlay, throughput and defectivity.
Imprint lithography, like any lithographic approach requires that defect mechanisms be identified and eliminated in
order to consistently yield a device. NIL has defect mechanisms unique to the technology, and they include liquid phase
defects, solid phase defects and particle related defects. Especially more troublesome are hard particles on either the
mask or wafer surface. Hard particles run the chance of creating a permanent defect in the mask, which cannot be
corrected through a mask cleaning process. If Cost of Ownership (CoO) requirements are to be met, it is critical to
minimize particle formation and extend mask life.
To meet the CoO requirements, mask life must meet or exceed 1000 wafers. If, we make the conservative assumption
that every particles causes damage to the mask pattern, the number of particle adders must be less than 0.001 pieces per
wafer pass in the NIL tool. Therefore, aggressive strategies are needed to reduce particles in the tool.
In this paper, we will report on the techniques required to meet this condition and will describe how the particle
reduction techniques can be extended to our FPA-1200NZ2C system.
Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is cross-linked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate.
Criteria specific to any lithographic process for the semiconductor industry include overlay, throughput and defectivity. The purpose of this paper is to describe the technology advancements made in the reduction of particle adders in an imprint tool.
Hard particles on a wafer or mask create the possibility of creating a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, test stand results demonstrate the potential for extending mask life to better than 1000 wafers.
Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and
Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist
deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows
into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV
radiation, and then the mask is removed, leaving a patterned resist on the substrate.
There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Defectivity
and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of
semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the
mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by
introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this
work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers.
On the mask side, a new replication tool, the FPA-1100 NR2 is introduced. Mask replication is required for
nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle
control, resolution and image placement accuracy. In this paper we discuss the progress made in both feature resolution
and in meeting the image placement specification for replica masks.
Water-based immersion technology has overcome various challenges and is starting to be used for the 45nm-node mass
production. However, even though immersion technology is being used in memory device production, significant
improvement in defect performance is needed before the technology can be used for logic devices. Canon has developed
an immersion exposure system, the FPA-7000AS7, with numerical aperture of 1.35. In the AS7 immersion tool, there is
little influence of vibration and evaporative cooling. The AS7 has an in-situ cleaning system in order to remove particles
carried into the exposure tool. We evaluated the contamination of the projection lens and immersion nozzle due to photoacid
generator (PAG) leaching from resist to water. We evaluated the cleaning effects of various cleaning processes and
found the suitable processes for cleaning the projection lens and immersion nozzle from the view that it does not
adversely affect the exposure tool: damage-free and easy drainage treatment. In addition, we evaluated the influence of
particles on the wafer stage, since there is a major concern that particles entering the water may increase the defects. The
number of particles adhering on the wafer during an exposure sequence can be reduced with the wafer stage cleaning.
Periodical cleaning keeps the wafer stage clean, thus preventing the increase of exposure defects caused by particles. We
performed a defect evaluation with the AS7. The average defect density was 0.042/cm2 in the continuous exposure
process of 25 wafers with a developer-soluble topcoat. Circle defects and bubble defects were not observed.
Water-based immersion technology has overcome various obstacles and is approaching the mass production phase.
Canon is in the process of developing an ArF immersion exposure tool, FPA-7000AS7 (NA>1.3), to meet both mass
production of the 65nm HP and development of the 45nm HP, which starts in 2007.
In the Canon immersion nozzle, there is little influence of vibration on the lens and the stage, and particle generation
from the nozzle during treatment of the nozzle in the manufacturing process has successfully been prevented.
We evaluated contamination due to leaching and cleaning technology with a test bench. Contamination due to PAG
(Photo-acid Generator) leaching from resist to water could be completely eliminated by dipping it into a cleaning fluid.
With periodic cleaning, it is possible to keep the projection lens clean and to prevent particle generation from the
immersion nozzle.
The defect was evaluated with FPA-6000AS4i (NA0.85) that had the same type of immersion nozzle as that of
FPA-7000AS7. The level of defect density was stable in a continuous exposure process of 25 wafers with a
developer-soluble topcoat. The defect density was 0.030/cm2 with a topcoat-less resist.
193-nm immersion lithography using water as the immersion fluid is the most promising technology candidate for achieving the 45nm HP node. We have been developing a high NA immersion exposure tool through collaboration with several companies in the industry. This paper presents the results we have obtained on various aspects of immersion exposure system development, and discusses the latest status on the issues that have been explored. In immersion lithography, leaching from resist raises concerns about lens contamination. Using a lens contamination test setup, we examined deposition that is formed on the lens surface when irradiated with a laser. It is estimated from the results that no contamination due to PAG will occur in the exposed area. The test results will be shown in detail. Using our immersion system, no defects have been found so far that are identified as bubble-induced. Therefore, we intentionally obtained bubble-induced defects by introducing micro bubbles into the immersion liquid. The findings will be discussed in this paper. Also, we established our "Immersion Evaluation Laboratory" to facilitate evaluation of all aspects of the immersion lithography process. The laboratory is equipped with (1) 193nm immersion scanner, FPA-6000AS4i with NA 0.85 and a 300mm wafer stage capable of 500mm/s scanning, (2) coater/developer, (3) defect inspection system and (4) SEM. We have performed full-wafer exposure tests using the AS4i, the result of which will be also presented.
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