In our previous paper, "Warpage of thin wafers using computer aided reflection moire method," the surface curvature
and residual stresses were evaluated using the versatility of computer aided reflection grating method to manipulate and
generate gratings in two orthogonal directions. A very good agreement between the theory and experimental results was
established. The bending stresses of wafers due to the deposition of backside metallization were evaluated without the
aid of reference grating.
In this paper, some aspects of the work is extended. An optical flat with flatness λ/10 is used as a reference plate to
extract the residual stress of the wafers with different backside metallization. By utilizing the phase information from the
moiré pattern between deformed grating (wafer) and undeformed grating (optical flat), the surface deformation of the
wafer and residual stresses are investigated quantitatively and numerically.
This technique, with satisfactory sensitivity and accuracy, can be used to characterize the residual stress of wafer due to
warpage that may lead to the crack issues in semiconductor manufacturing industry.
To cope with advances in the electronic packaging industry, thinner wafers are being widely employed to produce
thinner packages. However, this has lead to an increase in random cracks during the wafer singulation process, thus
reducing the yield of the overall production.
Large stresses are induced particularly during backside metal deposition. The wafers bend due to these stresses. This
residual stress due to warpage lead to cracks which will severely re-orient the residual stress distributions, thus,
weakening the mechanical and electrical properties of the singulated die.
In this study, Computer aided reflection moiré technique is adapted to further investigates the warpage induced on
wafers with different backside metallization (bare silicon, AuY, AuX). The backside metal on the wafer is then etched
to remove the residual stress. Residual stress due to the effect of warpage caused by different backside metallization has
been experimentally investigated and compared. Applicability of this technique to correlate with the random crack in
the die is further validated.
The ecomony scale of return for semiconductor wafers can be attributed to 2 factors i.e.1) number of systems that is
crammed onto a wafer and 2) substitution of precious metal (Au) to other material for the wafer backmetal. Any of these
2 changes will be a major challenge to semiconductor wafer dicing yield. Crack die with a random order is a great myth
to be dicovered. In this study, Moire Techniques is being adopted to perform the upfront analysis on the crack die to
minimize the yield loss during dicing process. In this study we focus and to corellate 3 different wafers with different
size (5", 6" and 8") and backmetal (bare silicon, Au and AuX). The effect of the backside metallization to the die
strength has been numerically and experimentally investigated. These results obtained is being made to optimise the
dicing method to obtain a homogenous stresses across the wafer.
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