In the realm of next-generation EUV masks, several material candidates show promising absorber behaviors, ranging from binary to phase-shift types. However, the mask repair process presents challenges when managing wafer windows for repaired defects. Precious profile control, high repair-defect durability and clean reticle surface need to be sustained to ensure lithography processes window. In this paper, several materials’ opaque defect etching is evaluated by using ZEISS e-beam based MeRiT® neXT repair tools, which offer an optimal physico-chemical process with right precursor chemistry and an optimized scanning of the e-beam over the surface to ensure repair quality. Moreover, longer repair time for next generation masks also challenges post-repair clean yield due to poor wettability from etching byproduct redeposition on reticle surface. Thus, we control a plasma flushing vacuum chamber application to eliminate surface wettability degradation, ensuring high post-repair clean yield. Our comprehensive strategy not only addresses current challenges with better reticle quality and longer lifetime but also paves the way for the seamless integration of advanced EUV mask materials into the future of semiconductor lithography.
With EUV reticle features shrinking and becoming more complicated, conventional 193 nm inspection tools pose significant challenges due to poor signal-to-noise (SNR) ratio, low optical image stability, and limited data processing capability. To meet these challenges, we have implemented machine learning techniques in EUV reticle inspection starting from advanced technology nodes, which effectively improve defect SNR and eliminates false counts. This accomplishment has been made possible through a combination of several innovations addressed in KLA’s third generation Teron™ 640e Series system: 1. Aberration Control Compensation Techniques: These techniques reduce intrinsic optical noise, enhancing accurate defect detection. 2. Focus drift improvement: Controlling focus drift within tens of nanometers through a full mask area scan is achieved by deploying high-frequency focus trajectory calibration and a low thermal expansion stage. 3. X30 Die-to-Database (DB) Inspection Mode: Leveraging Gen-2 deep learning algorithms, this encompasses a comprehensive analysis of layout dimensions and the integration of design elements through to the final pattern generation. The objective is to enhance the modeling process, thereby diminishing noise levels for superior inspection sensitivity. 4. Curvilinear-Friendly Geometry Classification Scheme: KLA-designed Gen-2 feature map for advanced inspection sensitivity control. 5. Enhanced Data Preparation Server: Efficiently handling data sizes of OASIS P49 MULTIGON format four times larger than traditional Manhattan formats, this server ensures comparable data preparation time. The 3rd generation Teron™ 640e Series system has been demonstrated to meet production requirements for N technology node and beyond. The next step will focus on cutting-edge optical and algorithm design to overcome resolution limitations and implementing these advanced technologies in the most suitable areas of EUV mask inspection.
The successful development of Actinic Pattern Mask Inspection (APMI) has enabled the high-volume manufacturing of advanced chips, such as N5 and N3, due to the production of defect-free masks by tsmc's mask shop. This accomplishment can be attributed to the utilization of an innovative Extreme Ultraviolet (EUV) inspector and Graphics Processing Unit (GPU)-based defect detection with Artificial Intelligence (AI) assistance. The application of EUV inspector unleashed pellicle inspection to prolong mask operation periods in wafer foundries. Besides, the improving in the manufacturing efficiency via automation also boost the productivity in the mask shop. According to our previous report in BACUS 2023, the improvement by performing various approaches in the novel Laser-Produced Plasma (LPP) system enabled tsmc to capture EUV image with high stability. The continual improving in the system in later keep reducing the vibration of the crucible and hence improve the tin stability. Furthermore, tsmc developed a GPU-based inspection system, which allowed for flexible algorithm development compared to FPGA. The ML-based rendering model aligned features with tool images and reduced image residue. Therefore, the final inspected image could be possessed with high SNR in advanced node and aggressive OPC compared to DUV inspector. Additionally, the final inspection results will be processed via a Deep Learning (DL) based model, reducing false positives, and implementing auto-defect classification. By combining these contributions, the actinic tools were able to streamline the manufacturing flow and fulfill the requirements for massive production significantly.
Given the successful development in actinic pattern mask inspection (APMI), high-volume manufacturing of advanced chips including N5 and N3 was realized due to the defect-free masks provided by the TSMC mask shop. This achievement was attributed to the newly developed EUV source and GPU-based defect detection with machine learning (ML) assistance. Unlike conventional approaches which sustain less than two weeks, the rotated crucible fed by Sn fuel in the LPP (Laser-produced plasma) system provided one month of operating stability with ultra-low tin consumption. The newly developed LPP EUV light source has been moved towards double IR power to produce higher EUV photon counts, resulting in better throughput and inspection sensitivity. It enables captured images to possess an effective signalto-noise ratio (SNR) and reasonable inspection nuisance counts. The common technique challenges, Sn auto-refuel and debris mitigation, were overcome by auto-refuel and reuse, debris mitigation, and plasma position control. Moreover, the LPP system also showed its capability in performing pellicle inspection to prolong mask operation periods in wafer foundries. For the GPU-based inspection system, it provided the feasibility and flexibility in algorithm development compared to the FPGA approach. The TSMC developed machine-learning (ML) based rendering model played a key role in aligning features with tool images in D2D mode, as well as residue reduction of D2DB mode. All rendering models were implemented by CUDA coding and running on TSMC-customized GPU architecture to fulfill the goal of high-speed computation and defect capture rate that met production specifications. Combining with the ML model, proper detectors were designed for each specific feature, such as SRAF and curvy OPC design, and the performance of auto defect classification (ADC) with the model has been proven. By integrating all the work, it enabled the actinic tools to fulfill the requirement of massive production significantly.
The EUV reticle masking process has enabled the creation of smaller and more intricate integrated circuits, which are essential components of modern electronic devices. However, ensuring defect-free control and evaluation in the cutting-edge EUV reticle masking process is a challenging task. Currently, every potential defect must be judged by wafer printing assessment for almost 3 days, which can be both time-consuming and expensive, and even commercial approaches are incapable of meeting the demands of high-volume manufacturing. In this paper, we successfully developed the EUV Actinic Mask Review System (AMRS) to emulate wafer printability behaviors, utilizing a stable LPP EUV source with over 95% available time and a specialized TSMC-made SMO to achieve high throughput for more than 80 sites/hr. In addition, various EUV resist models have been developed to emulate the risk defect printing assessment with good matching results, and an in-house automation EUV defect analysis platform was developed to achieve fast and accurate areal image measurement. With this solution, all EUV repaired and potential defects, including 18nm HP L/S, ML defects, and even through EUV pellicle defects, can be addressed in technology nodes N5, N3, and beyond N3, on the brand-new actinic review platform. The development of the EUV Actinic Mask Review System represents a significant advancement in ensuring the quality and reliability of semiconductor devices. It provides a practical solution to the challenges posed by the EUV reticle masking process and enables the production of defect-free integrated circuits, paving the way for the continued innovation and progress of the semiconductor industry.
EUV lithography is a key technology in the semiconductor industry and using pellicle that protects reticle from contamination during lithography process has become increasingly important. In this paper, different types of pellicles showing 82~>95% EUV transmittance and wafer moves 5K~50k under different transmittances, scanner powers and resists have been demonstrated for high volume wafer production at this work. For pellicle particle quality, we developed new inspection tool to achieve >1um pinhole-free and with significant defectivity reduction compared to previous one. Almost no fall-on rate is validated for real wafer production. Furthermore, this work develops full infrastructure, which include pellicle-making, pellicle-mounting and through pellicle inspection are validated to provide simple and robust production capability. Our EUV pellicle frame design shows fully compatibility with advanced 193nm reticle pelliclemounting process. Now previous EUV pellicle solution is ready to support advanced nodes application. The other key indices for high wafer throughput and cost reduction are high pellicle transmittance and durability. The pellicle optical performances (EUV transmittance, EUVT uniformity and EUV reflectance) are comparable to the previous solution. Moreover, no negative effects on wafer critical dimension uniformity (CDU) regarding to mask with and without pellicle mounting. In this work, a high-volume manufacturing (HVM) EUV pellicle with excellent defect and durability have been successfully qualified for the needs of advanced node productions.
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