Dr. Victor Vega Gonzalez Profile

Dr. Victor Vega Gonzalez

at imec

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Publications (6)

Proceedings Article | 9 April 2024 Presentation + Paper

Dry etch challenges for patterning middle-of-line (MOL) contact trench in monolithic CFET (complementary FET)

T. Sarkar, D. Radisic, V. Vega Gonzalez, K. Stiers, C. Sheng, D. Montero, H. Jenkins, M. Demand, P. Wang, F. Lazzarino, N. Horiguchi

Proceedings Volume 12958, 129580B (2024) https://doi.org/10.1117/12.3014213

KEYWORDS: Etching, Optical lithography, Polymers, Semiconducting wafers, Plasma etching, Passivation, Lithography, Plasma, Dry etching, Wafer testing

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Proceedings Article | 1 May 2023 Presentation + Paper

Middle-of-line plasma dry etch challenges for CFET integration

D. Radisic, M. Hosseini, H. Mertens, D. Zhou, V. Vega Gonzalez, S. Wang, B. Chan, D. Batuk, E. Dupuy, Z. Tao, E. Dentoni Litta, N. Horiguchi

Proceedings Volume 12499, 1249909 (2023) https://doi.org/10.1117/12.2659095

KEYWORDS: Etching, Optical lithography, Lithography, Plasma etching, Plasma, Dry etching, Critical dimension metrology, Dielectrics

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In this paper, middle-of-line (MOL) plasma etch development results for the monolithic CFET integration with nanosheet devices using scaling-relevant test vehicle (CPP48nm) are presented. Several critical MOL patterning steps are addressed, with the focus on the patterning of the trenches (M0) for contacting to the bottom and top devices. The patterning of M0A consists of SiO₂ dielectric and thin SiN liner etch landing on epitaxial source drain (S/D). The critical M0 etch requirement is preserving the SiN gate spacer to avoid shorting between S/D and gate. Due to no-gate plug implementation in the process flow, the etch development must rely on very challenging, patterning the small critical dimension (CD) contacts to create enough dielectric barrier between the metal contact and the gate, and preferably, also very challenging, self-alignment to the thin gate spacer. The dependance of the M0 CD and the etch depth is accessed by using the range of the EUV lithography conditions and evaluating the maximum etch depth of the trench as a function of the printed CD. The minimum trench CD achieved on the bottom of the trench is ~ 13nm, and the minimum top CD in the range of ~ 16nm, with the evident etch non-uniformity observed in the etch depth. The trend of larger contact CD resulting in the deeper etch and process uniformity improvement is observed. Etch depth larger than 100nm is achieved when top M0 CD is >20nm. The option with the SiN liner deposition followed by SiN liner etch (spacer formation) post- M0 SiO₂ is developed. This patterning sequence consists of SiO₂ etch stopping on the thin SiN (over S/D) followed by additional SiN deposition and finally etching of the deposited SiN liner as well as SiN liner covering S/D. The option with SiN spacer formation minimizes the risk of short to the gate, due to extra SiN dielectric film protecting the gate. In addition, we present the results for another critical MOL patterning step, i.e., HAR metal recess post M0 metallization (AR~11)

Proceedings Article | 28 April 2023 Poster + Paper

Cost analysis of device options and scaling boosters below the A14 technology node

G. Mirabelli, A. Vandooren, C. Roda Neve, V. Gonzalez, H. Mertens, A. Farokhnejad, P. Schuddinck, G. Murdoch, S. Salahuddin, O. Zografos, L. Ragnarsson, P. Weckx, Z. Tokei, G. Hellings, J. Ryckaert

Proceedings Volume 12495, 124951K (2023) https://doi.org/10.1117/12.2656456

KEYWORDS: Semiconducting wafers, Metals, Back end of line, Silver, Optical lithography, Transmission electron microscopy, Nanosheets, Front end of line, Wafer bonding, Semiconductors

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Proceedings Article | 27 April 2023 Presentation + Paper

In-line metrology for vertical edge placement control of monolithic CFET using CD-SEM

Wei Sun, Ayumi Doi, Miki Isawa, Victor Vega Gonzalez, Zsolt Tokei, Gian Lorusso

Proceedings Volume 12496, 124961V (2023) https://doi.org/10.1117/12.2656471

KEYWORDS: Transmission electron microscopy, Semiconducting wafers, Metrology, Etching, Monte Carlo methods, Critical dimension metrology, Calibration, Wafer bonding, Signal intensity, Optical lithography

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Proceedings Article | 26 May 2022 Presentation + Paper

Design, patterning, and process integration overview for 2nm node

Syed Muhammad Yasser Sherazi, Yi-Han Chang, Youssef Drissi, Bilal Chehab, Jae Uk Lee, Victor Vega Gonzales, Ryan Ryoung Han Kim

Proceedings Volume 12052, 120520F (2022) https://doi.org/10.1117/12.2615311

KEYWORDS: Metals, Fin field effect transistors, Semiconducting wafers, Optical lithography, 3D imaging standards, Integrated circuits, CMOS devices, Standards development, Field effect transistors, Etching

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Proceedings Article | 7 April 2017 Presentation + Paper

Self-aligned block technology: a step toward further scaling

Frédéric Lazzarino, Nihar Mohanty, Yannick Feurprier, Lior Huli, Vinh Luong, Marc Demand, Stefan Decoster, Victor Vega Gonzalez, Julien Ryckaert, Ryan Ryoung Han Kim, Arindam Mallik, Philippe Leray, Chris Wilson, Jürgen Boemmels, Kaushik Kumar, Kathleen Nafus, Anton deVilliers, Jeffrey Smith, Carlos Fonseca, Julie Bannister, Steven Scheer, Zsolt Tokei, Daniele Piumi, Kathy Barla

Proceedings Volume 10149, 1014908 (2017) https://doi.org/10.1117/12.2258028

KEYWORDS: Optical lithography, Etching, Photomasks, Double patterning technology, Extreme ultraviolet, Semiconductors, High volume manufacturing, Metals, Standards development, Lithography, Amorphous silicon, Coating, System on a chip, Materials processing, Silica, Tin

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Showing 5 of 6 publications

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