Dr. Odysseas Zografos Profile

Dr. Odysseas Zografos

at imec

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Author

Publications (9)

Proceedings Article | 10 April 2024 Presentation + Paper

Investigation of die-cost scaling scenarios in future technologies

G. Mirabelli, Y.-P. Tsai, Y.-H. Chang, D. Velenis, R.-H. Kim, J. Myers, L.-Å. Ragnarsson, O. Zografos, G. Hellings

Proceedings Volume 12954, 129540E (2024) https://doi.org/10.1117/12.3010149

KEYWORDS: Semiconductor manufacturing, Back end of line, Logic, Front end of line

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Proceedings Article | 10 April 2024 Presentation + Paper

High-density standard cell libraries with backside power options in A14 nanosheet node

Halil Kükner, Gioele Mirabelli, Sheng Yang, Yun Zhou, Alexander Makarov, Yang Xiang, Juergen Boemmels, Anabela Veloso, Odysseas Zografos, Pieter Weckx, Julien Ryckaert, Geert Hellings

Proceedings Volume 12954, 1295409 (2024) https://doi.org/10.1117/12.3010866

KEYWORDS: Nanosheets, Design, Logic, Electronic design automation, Oscillators, Silicon, CMOS devices, Digital electronic circuits

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Proceedings Article | 10 April 2024 Presentation + Paper

2D local interconnect metal patterning exploration for CFET

Hsinlan Chang, Youssef Drissi, Gioele Mirabelli, Odysseas Zografos, Yasser Sherazi, Julien Ryckaert, Gaspard Hiblot

Proceedings Volume 12953, 129530Y (2024) https://doi.org/10.1117/12.3010804

KEYWORDS: Extreme ultraviolet, Printing, Optical lithography, Extreme ultraviolet lithography, Metals, Transistors, Optical proximity correction, Deep ultraviolet

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Proceedings Article | 28 April 2023 Poster + Paper

Cost analysis of device options and scaling boosters below the A14 technology node

G. Mirabelli, A. Vandooren, C. Roda Neve, V. Gonzalez, H. Mertens, A. Farokhnejad, P. Schuddinck, G. Murdoch, S. Salahuddin, O. Zografos, L. Ragnarsson, P. Weckx, Z. Tokei, G. Hellings, J. Ryckaert

Proceedings Volume 12495, 124951K (2023) https://doi.org/10.1117/12.2656456

KEYWORDS: Semiconducting wafers, Metals, Back end of line, Silver, Optical lithography, Transmission electron microscopy, Nanosheets, Front end of line, Wafer bonding, Semiconductors

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Proceedings Article | 28 April 2023 Poster + Paper

Physical design level PPA evaluation of buried power rail at 2nm node

Giuliano Sisto, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert

Proceedings Volume 12495, 124951X (2023) https://doi.org/10.1117/12.2656337

KEYWORDS: Design and modelling, Metals, Silicon, Electronic design automation, Nanosheets, Back end of line, Simulations, Resistance, Dielectrics, Tungsten

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Proceedings Article | 28 April 2023 Presentation + Paper

Design-technology co-optimization overview of CFET architecture

G. Mirabelli, P. Schuddinck, H.-H. Liu, S. Yang, O. Zografos, S. Salahuddin, P. Weckx, G. Hiblot, G. Hellings, J. Ryckaert

Proceedings Volume 12495, 124950M (2023) https://doi.org/10.1117/12.2657726

KEYWORDS: Semiconducting wafers, Back end of line, Nanosheets, Logic, Standards development, Metals, Fin field effect transistors, Semiconductors, Optical lithography, Nanotechnology

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Proceedings Article | 28 April 2023 Presentation + Paper

System-level evaluation of 3D power delivery network at 2nm node

Giuliano Sisto, Rongmei Chen, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert

Proceedings Volume 12495, 124950Y (2023) https://doi.org/10.1117/12.2656469

KEYWORDS: Metals, Design and modelling, 3D acquisition, Wafer bonding, Dysprosium, Back end of line, Semiconducting wafers, Electronic design automation, Logic, 3D image capture

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Proceedings Article | 26 May 2022 Paper

Logic via printability enhancement using restricted via placement and exhaustive SRAF placement on a staggered grid

Pieter Wöltgens, Alberto Colina, David Rio, Maxence Delorme, Tatiana Kovalevich, Arame Thiam, Frieda van Roey, Odysseas Zografos

Proceedings Volume 12051, 120510I (2022) https://doi.org/10.1117/12.2614260

KEYWORDS: SRAF, Logic, Semiconducting wafers, Lithography, Photomasks, Optical proximity correction, Critical dimension metrology, Printing, Extreme ultraviolet lithography, Statistical analysis

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Proceedings Article | 27 March 2019 Presentation + Paper

Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet

S. M. Yasser Sherazi, Miroslav Cupak, P. Weckx, O. Zografos, D. Jang, P. Debacker, D. Verkest, A. Mocuta, R. H. Kim, A. Spessot, J. Ryckaert

Proceedings Volume 10962, 1096202 (2019) https://doi.org/10.1117/12.2514569

KEYWORDS: Metals, Optical lithography, Fin field effect transistors, Extreme ultraviolet, Standards development, Silicon, Line edge roughness, Computer architecture, Process control

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Showing 5 of 9 publications

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