Ms. Angélique Raley Profile

Angélique Raley

Director BU Marketing at Tokyo Electron America, inc

SPIE Involvement:

Conference Program Committee | Author

Publications (24)

Proceedings Article | 20 June 2023 Presentation + Paper

Presentation + Paper

Advanced process technologies for photonics waveguide patterning

Erik Geiss, Massud Aminpur, Ryan Sporer, Vijayalakshmi Seshachalam, Padraig Timoney, Brendan O'Brien, Josh LaRose, Eitan Barlaz, Cameron Werner, Katie Lutker-Lee, Luis Fernandez, Brian Pfeifer, Chimaobi Mbanaso, Yan Shao, Angélique Raley

Proceedings Volume PC12499, PC124990B (2023) https://doi.org/10.1117/12.2657729

KEYWORDS: Semiconducting wafers, Waveguides, Etching, Atomic layer deposition, Plasma etching, Plasma, Line edge roughness, Silicon, Vacuum ultraviolet, Film thickness

Read Abstract +

Proceedings Article | 30 April 2023 Presentation

Presentation

Challenges and innovations in EUV patterning: lithography and etch outlook

Eric Liu, Akiteru Ko, Sophie Thibaut, Katie Lutker-Lee, Steven Grzeskowiak, Alexandra Krawicz, Christopher Cole, Hamed Hajibabaei, Sergey Voronin, Nayoung Bae, Angelique Raley, Lior Huli, Kanzo Kato, David Hetzer, Kathleen Nafus, Seiji Fujimoto, Seiji Nagahara, Satoru Shimura, Shinichiro Kawakami, Congque Dinh, Yuhei Kuwahara, Shigeru Tahara, Masanobu Honda, Tetsuya Nishizuka, Peter Biolsi, Hiromasa Mochiki

Proceedings Volume PC12499, PC124990H (2023) https://doi.org/10.1117/12.2659720

KEYWORDS: Etching, Optical lithography, Lithography, Extreme ultraviolet, Plasma etching, Plasma, Transistors, Semiconducting wafers, Photoresist processing, Photochemistry

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Proceedings Article | 13 June 2022 Presentation

Presentation

Patterning options for post-copper metallization on EUV self-aligned double patterning method

Eric Liu, Joe Lee, Nicholas Joy, Yann Mignot, Angelique Raley, John Arnold, Peter Biolsi

Proceedings Volume PC12056, PC1205609 (2022) https://doi.org/10.1117/12.2615458

KEYWORDS: Optical lithography, Metals, Copper, Photomasks, Extreme ultraviolet, Etching, Double patterning technology, Dielectrics, Atomic layer deposition, Transition metals

Read Abstract +

For more than two decades and through approximately ten technology nodes, the semiconductor industry has relied upon Dual Damascene copper interconnects. While there is vigorous debate as to the timing and dimensions of the transition, there is a general consensus that there will eventually be a need to replace copper with a different conductor metal. Motivations include copper’s requirement for space-consuming diffusion barriers and the contributions of interfacial electron scattering to higher resistance at smaller dimensions. Researchers such as D. Galla have proposed a range of candidate conductor metals, many of which would be patterned subtractively (by depositing blanket sheets of material and then etching away the portions not required for circuity). There is a growing body of literature considering the choice of metal, methods for controlling its morphology and electrical behavior, and processes for etching it. In this study, we examine a different facet of the transition from Damascene to subtractive conductor formation, specifically the role played by sidewall spacers in pattern formation and transfer. Because the dimensions at which non-Cu conductors may become competitive are well beyond the resolution limits of single exposure EUV, it is likely that an SADP process will be used. The common approach to pattern assembly for Damascene applications is to place mandrels where Cu conductors are ultimately desired, use ALD spacers on the mandrel sidewalls to define minimum-width dielectric spaces, then add a block pattern to define larger regions of dielectric and the remaining “non-mandrel” or “anti-mandrel” conductors. Then the mandrels are removed and the openings in the spacer+block mask are transferred into the dielectric, forming the trenches which will ultimately be filled with Cu. For subtractive metal patterning, preserving the existing circuit design and mask generating infrastructure favors a different approach: mandrels would still be placed at conductor locations and ALD spacers would still be used to define minimum dielectric spaces, but anti-mandrel conductor locations would be covered by new regions of masking material (rather than openings in the block mask). Then the spacers would be removed and the mandrels and anti-mandrel masks would be used to transfer the pattern into the metal below. This study focuses on comparison of the patterning performance of the two approaches using model structures to minimize the confounding impact of the subsequent etch steps (i.e., etching into ULK or metal). Topics of particular interest include LER, LWR, CDU, pitchwalking, and the effects of local variations in pattern density. Methods to improve patterning performance for both schemes will be discussed.

Proceedings Article | 25 May 2022 Presentation + Paper

Presentation + Paper

Outlook for high-NA EUV patterning: a holistic patterning approach to address upcoming challenges

Angélique Raley, Lior Huli, Steven Grzeskowiak, Katie Lutker-Lee, Alexandra Krawicz, Yannick Feurprier, Eric Liu, Kanzo Kato, Kathleen Nafus, Arnaud Dauendorffer, Nayoung Bae, Josh LaRose, Andrew Metz, Dave Hetzer, Masanobu Honda, Tetsuya Nishizuka, Akiteru Ko, Soichiro Okada, Yasuyuki Ido, Tomoya Onitsuka, Shinichiro Kawakami, Seiji Fujimoto, Satoru Shimura, Cong Que Dinh, Makoto Muramatsu, Peter Biolsi, Hiromasa Mochiki, Seiji Nagahara

Proceedings Volume 12056, 120560A (2022) https://doi.org/10.1117/12.2613063

KEYWORDS: Plasma etching, Etching, Extreme ultraviolet, Optical lithography, Plasma, Focus stacking software, Semiconducting wafers, Photoresist processing, Extreme ultraviolet lithography, Silicon carbide

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Proceedings Article | 28 September 2021 Poster + Presentation

Poster + Presentation

Coater/developer and new underlayer application to sub-30nm process

Kanzo Kato, Naoki Shibata, Lior Huli, Dave Hetzer, Angélique Raley, Christopher Cole, Alexandra Krawicz, Satoru Shimura, Shinichiro Kawakami, Soichiro Okada, Takahiro Kitano, Akihiro Sonoda, Karen Petrillo, Luciana Meli, Cody Murray, Alex Hubbard

Proceedings Volume 11854, 118541D (2021) https://doi.org/10.1117/12.2602829

KEYWORDS: Optical lithography, Extreme ultraviolet, Photoresist processing, Oxides, Metals, Lithography, Integrated circuits, Extreme ultraviolet lithography, Etching

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SPIE Journal Paper | 17 June 2021

Line edge roughness reduction for EUV self-aligned double patterning by surface modification on spin-on-carbon and tone inversion technique

Eric Liu, Katie Lutker-Lee, Qiaowei Lou, Ya-Ming Chen, Angélique Raley, Peter Biolsi, Kai-Hung Yu, Gregory Denbeaux

JM3, Vol. 20, Issue 02, 024901, (June 2021) https://doi.org/10.1117/12.10.1117/1.JMM.20.2.024901

KEYWORDS: Line edge roughness, System on a chip, Extreme ultraviolet, Plasma, Etching, Lithography, Silicon, Double patterning technology, Line width roughness, Extreme ultraviolet lithography

Read Abstract +

Extreme ultraviolet lithography (EUVL) has been adopted into high volume production for advanced logic device manufacturing. Due to the continuous size scaling requirement for interconnect fabrication, EUVL with self-aligned double patterning (SADP) formation has attracted substantial research attention. The current challenge in EUV SADP is the pattern transfer process from lithography to mandrel formation. In this step, the target critical dimension (CD) of the feature needs to shrink by half from the lithography CD during the etch process. The increasing aspect ratio during this etch potentially deteriorates the pattern validity and the line edge roughness (LER). In addition to these challenges, EUVL has a fundamental bottleneck due to stochastic effects, which can lead to device degradation by defect formation and edge placement error (EPE). LER of the line and space pattern is one of the main contributors to EPE. Effective methods of LER reduction in both process and integration are needed in order to reduce pattern variation and boost device performance. In our study, we examine a technique to reduce LER on the EUV SADP line pattern. This technique involves the surface modification on the spin-on carbon (SOC) layer in the patterning stack and tone inversion process. We had found a trend between surface hydrophobicity of the SOC and the EUV SADP LER performance. The condition that increased the hydrophobicity of the SOC resulted in a lower LER performance after tone inversion. The tested conditions include direct current superposition (DCS) function with H2 plasma, fluorocarbon plasma, and the combination of DCS with H2 plasma and trimethylsilane dimethylamine deposition. On 20-nm pitch EUV SADP, this technique shows 26% of LER improvement from lithography to SADP formation. PSD analysis recorded about 6% and 30% of the LER improvement at the correlation length of >200 nm and 200 to 30 nm, respectively. A demonstration of this technique for a further scaling to 15-nm pitch also shows an LER reduction of 30% from lithography to SADP formation.

Proceedings Article | 9 April 2021 Presentation + Paper

Presentation + Paper

Line edge roughness (LER) reduction strategies for EUV self-aligned double patterning (SADP)

Eric Liu, Katie Lutker-Lee, Qiaowei Lou, Ya-Ming Chen, Angélique Raley, Peter Biolsi

Proceedings Volume 11615, 1161506 (2021) https://doi.org/10.1117/12.2582556

Read Abstract +

Extreme ultraviolet lithography (EUVL) has been adopted into high volume production for advanced logic device manufacturing. Due to the continuous size scaling requirement for interconnect fabrication, EUVL with self-aligned double patterning (SADP) formation has attracted substantial research attention [1]–[6]. Double patterning techniques in EUVL achieve pitch halving in the final feature by using the spacer defined approach and self-aligned block (SAB) mitigates the block placement error by leveraging etch selectivities and material filling capability. The current challenge in EUV SADP is the pattern transfer process from lithography to mandrel formation. In this step, the target critical dimension (CD) of the feature needs to shrink by half from the lithography CD during the etch process. The increasing aspect ratio during this etch potentially deteriorates the pattern validity and the line edge roughness (LER) [5]. In addition to these challenges, EUVL has a fundamental bottleneck due to stochastic effects which can lead to device degradation by defect formation and edge-placement-error (EPE) [7]–[10]. LER of the line and space pattern is one of the main contributors to EPE. Effective methods of LER reduction in both process and integration are needed in order to reduce pattern variation and boost device performance. In our research, we examine three approaches to reduce LER on the EUV SADP line pattern. This includes photoresist surface smoothing techniques, patterning layer material study, and tone inversion integration. The photoresist surface smoothing techniques involve a specific plasma process on the EUV chemical amplified resist (CAR) to achieve > 15% of improvement on LER from lithography to post etch performance. The patterning layer material study reveals an optimum patterning stack to minimize etch-induced line wiggling and etch selectivity requirements for LER performance. Finally, a first demonstration of EUV SADP tone inversion process integration is presented as a method to provide additional benefits to LER reduction. A detailed analysis of line performance from each processing step will be examined.

Proceedings Article | 26 February 2021 Presentation + Paper

Presentation + Paper

Contact local CD uniformity optimization through etch shrink

Eric Miller, Junling Sun, Jennifer Church, Xinghua Sun, Angelique Raley

Proceedings Volume 11615, 116150A (2021) https://doi.org/10.1117/12.2583666

KEYWORDS: Etching, Critical dimension metrology, Optical lithography, Back end of line, Semiconducting wafers, Logic, Lithography, Dielectrics

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Proceedings Article | 22 February 2021 Presentation + Paper

Presentation + Paper

Novel bottom-up organic mandrel growth to enable organic mandrel EUV SADP for sub-5nm node technologies

Katie Lutker-Lee, Emma Richardson, David O'Meara, Angélique Raley

Proceedings Volume 11615, 1161507 (2021) https://doi.org/10.1117/12.2583426

KEYWORDS: Extreme ultraviolet, Etching, Extreme ultraviolet lithography, Semiconducting wafers, Lithography, Line edge roughness, Silicon, Photoresist materials, Double patterning technology

Read Abstract +

As EUV direct patterning begins to hit its resolution limit, the need for EUV self-aligned double patterning (SADP) has arisen in order to reach sub-30 nm pitch. Currently, EUV resists suffer from several shortcomings, both in terms of roughness and resist budget. These constraints means using it directly as a mandrel material, as previously done for immersion lithography SADP is nearly impossible. Consequently, standard EUV SADP flows involve the transfer of the resist through a lithography stack and into a hard mandrel material, such as silicon nitride or amorphous silicon.¹ Achieving line edge roughness (LER) and line width roughness (LWR) targets for an EUV SADP hard mandrel is significantly more challenging than for EUV direct print since the etch process needs to target a post etch CD of about half that of the lithographic CD. This aggressive shrink requirement usually involves degradation in roughness driven by high aspect ratios. To circumvent these issues, we have developed a new bottom up organic mandrel growth process, whereby the EUV resist can be grown to a height compatible with a resist mandrel SADP flow, while the roughness is improved and the critical dimension is controlled. This bottom up mandrel growth process is performed in an etch chamber and can therefore be easily coupled with other process steps. The mandrel height and critical dimensions can be easily tuned from the incoming lithography by changing the deposition and trim step times of the process. We have shown that this bottom-up grown mandrel can withstand typical ALD spacer process deposition. After spacer open, the organic material can be easily removed through an in-situ ash process before opening the underlayer. This integration will allow for the removal of the organic planarizing layer in the lithography stack, reducing the stack complexity, while also eliminating one of the major contributors to wiggling in the typical hard mandrel patterning scheme. In this paper, the performance of this new integration scheme was benchmarked against a more standard SADP flow. The roughness performance post mandrel formation and post spacer deposition for this new scheme is significantly improved over our standard EUV SADP baseline using a standard EUV SADP flow.

Proceedings Article | 6 April 2020 Presentation + Paper

Presentation + Paper

Strategies for aggressive scaling of EUV multi-patterning to sub-20 nm features

Ashim Dutta, Jennifer Church, Joe Lee, Brendan O’Brien, Luciana Meli, Chi Chun Liu, Saumya Sharma, Karen Petrillo, Cody Murray, Eric Liu, Katie Lutker-Lee, Qiaowei Lou, Chris Cole, Angélique Raley, Akiteru Ko, Subhadeep Kal, Jake Kaminsky, Aelan Mosden, Henan Zhang, Shan Hu, Lior Huli, Naoki Shibata, Dave Hetzer, Chia-Yun (Sharon) Hsieh

Proceedings Volume 11323, 113230V (2020) https://doi.org/10.1117/12.2551727

KEYWORDS: Line edge roughness, Lithography, Etching, Amorphous silicon, Extreme ultraviolet, Oxidation, Extreme ultraviolet lithography, Optical lithography, Scanning electron microscopy, Critical dimension metrology

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Proceedings Article | 3 April 2020 Presentation + Paper

Presentation + Paper

Improvement of self-aligned dual patterning using spin-on-carbon mandrel

Caitlin Philippi, Sophie Thibaut, Andrew Metz, Akiteru Ko, Angélique Raley, Peter Biolsi

Proceedings Volume 11329, 113290T (2020) https://doi.org/10.1117/12.2550987

KEYWORDS: Etching, Carbon, Extreme ultraviolet lithography, Optical lithography, Lithography

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Proceedings Article | 25 November 2018 Paper

Paper

Benchmarking of EUV lithography line/space patterning versus immersion lithography multipatterning schemes at equivalent pitch

Angélique Raley, Chris Mack, Sophie Thibaut, Eric Liu, Akiteru Ko

Proceedings Volume 10809, 1080915 (2018) https://doi.org/10.1117/12.2501680

KEYWORDS: Line width roughness, Line edge roughness, Extreme ultraviolet, Optical lithography, Image filtering, Scanning electron microscopy, Etching, Photomasks, Lithography, Extreme ultraviolet lithography

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SPIE Journal Paper | 31 July 2018

Self-aligned blocking integration demonstration for critical sub-30-nm pitch Mx level patterning with EUV self-aligned double patterning

Angélique Raley, Joe Lee, Jeffrey Smith, Xinghua Sun, Richard Farrell, Jeffrey Shearer, Yongan Xu, Akiteru Ko, Andrew Metz, Peter Biolsi, Anton Devilliers, John Arnold, Nelson Felix

JM3, Vol. 18, Issue 01, 011002, (July 2018) https://doi.org/10.1117/12.10.1117/1.JMM.18.1.011002

KEYWORDS: Etching, Extreme ultraviolet, Line edge roughness, Optical lithography, Line width roughness, Silicon, Double patterning technology, Dielectrics, Metals, System on a chip

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Proceedings Article | 17 April 2018 Paper

Paper

EUV patterning using CAR or MOX photoresist at low dose exposure for sub 36nm pitch

Sophie Thibaut, Angélique Raley, Frederic Lazarrino, Ming Mao, Danilo De Simone, Daniele Piumi , Kathy Barla, Akiteru Ko, Andrew Metz, Kaushik Kumar, Peter Biolsi

Proceedings Volume 10589, 105890M (2018) https://doi.org/10.1117/12.2300355

KEYWORDS: Etching, Photoresist materials, Chemistry, Carbon, Line edge roughness, Lithography, Line width roughness, Extreme ultraviolet lithography, Scanning electron microscopy, Plasma enhanced chemical vapor deposition

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Proceedings Article | 9 April 2018 Paper

Paper

Multi-color fly-cut-SAQP for reduced process variation

Richard Farrell, Elliott Franke, Kanda Tapily, Jodi Hotalen, David O'Meara, Angelique Raley, Akitero Ko, Peter Biolsi, Cory Wajda, Gert Leusink, Anton DeVilliers, David Hetzer

Proceedings Volume 10586, 1058611 (2018) https://doi.org/10.1117/12.2303004

KEYWORDS: Etching, Plasma etching, Chemical mechanical planarization, Optical lithography, Plasma, Lithography, Transmission electron microscopy, Silica, Polishing, Critical dimension metrology

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Proceedings Article | 4 April 2018 Paper

Paper

Self-aligned blocking integration demonstration for critical sub-30nm pitch Mx level patterning with EUV self-aligned double patterning

Angélique Raley, Joe Lee, Jeffrey Smith, Xinghua Sun, Richard Farrell, Jeffrey Shearer, Yongan Xu, Akiteru Ko, Andrew Metz, Peter Biolsi, Anton Devilliers, John Arnold, Nelson Felix

Proceedings Volume 10589, 105890L (2018) https://doi.org/10.1117/12.2297438

KEYWORDS: Etching, Extreme ultraviolet, Line edge roughness, Image processing, Optical lithography, Dielectrics, Silicon, Metals, Line width roughness, Double patterning technology

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SPIE Journal Paper | 28 August 2017

Ultrathin extreme ultraviolet patterning stack using polymer brush as an adhesion promotion layer

Indira Seshadri, Anuja De Silva, Luciana Meli, Chi-Chun Charlie Liu, Cheng Chi, Jing Guo, Hoa Truong, Kristin Schmidt, John Arnold, Nelson Felix, Lovejeet Singh, Tsuyoshi Furukawa, Ramakrishnan Ayothi, Angelique Raley, Richard Farrell

JM3, Vol. 16, Issue 03, 033506, (August 2017) https://doi.org/10.1117/12.10.1117/1.JMM.16.3.033506

KEYWORDS: Oxides, Polymers, Extreme ultraviolet, Optical lithography, Head-mounted displays, Etching, Atomic layer deposition, Chemistry, Plasma enhanced chemical vapor deposition, Printing

Read Abstract +

Proceedings Article | 27 April 2017 Presentation

Presentation

Dry-plasma-free chemical etch technique for variability reduction in multi-patterning (Conference Presentation)

Subhadeep Kal, Nihar Mohanty, Richard Farrell, Elliott Franke, Angelique Raley, Sophie Thibaut, Cheryl Pereira, Karthik Pillai, Akiteru Ko, Aelan Mosden, Peter Biolsi

Proceedings Volume 10149, 101490P (2017) https://doi.org/10.1117/12.2257507

KEYWORDS: Etching, Plasma, Plasma etching, Optical lithography, Wet etching, Back end of line, Front end of line, Line edge roughness, Chemistry, Line width roughness

Read Abstract +

Scaling beyond the 7nm technology node demands significant control over the variability down to a few angstroms, in order to achieve reasonable yield. For example, to meet the current scaling targets it is highly desirable to achieve sub 30nm pitch line/space features at back-end of the line (BEOL) or front end of line (FEOL); uniform and precise contact/hole patterning at middle of line (MOL). One of the quintessential requirements for such precise and possibly self-aligned patterning strategies is superior etch selectivity between the target films while other masks/films are exposed. The need to achieve high etch selectivity becomes more evident for unit process development at MOL and BEOL, as a result of low density films choices (compared to FEOL film choices) due to lower temperature budget. Low etch selectivity with conventional plasma and wet chemical etch techniques, causes significant gouging (un-intended etching of etch stop layer, as shown in Fig 1), high line edge roughness (LER)/line width roughness (LWR), non-uniformity, etc. In certain circumstances this may lead to added downstream process stochastics. Furthermore, conventional plasma etches may also have the added disadvantage of plasma VUV damage and corner rounding (Fig. 1). Finally, the above mentioned factors can potentially compromise edge placement error (EPE) and/or yield.

Therefore a process flow enabled with extremely high selective etches inherent to film properties and/or etch chemistries is a significant advantage. To improve this etch selectivity for certain etch steps during a process flow, we have to implement alternate highly selective, plasma free techniques in conjunction with conventional plasma etches (Fig 2.). In this article, we will present our plasma free, chemical gas phase etch technique using chemistries that have high selectivity towards a spectrum of films owing to the reaction mechanism ( as shown Fig 1). Gas phase etches also help eliminate plasma damage to the features during the etch process. Herein we will also demonstrate a test case on how a combination or plasma assisted and plasma free etch techniques has the potential to improve process performance of a 193nm immersion based self aligned quandruple patterning (SAQP) for BEOL compliant films (an example shown in Fig 2). In addition, we will also present on the application of gas etches for (1) profile improvement, (2) selective mandrel pull (3) critical dimension trim of mandrels, with an analysis of advantages over conventional techniques in terms of LER and EPE.

Proceedings Article | 26 April 2017 Presentation + Paper

Presentation + Paper

EPE improvement thru self-alignment via multi-color material integration

Nihar Mohanty, Jeffrey Smith, Lior Huli, Cheryl Pereira, Angelique Raley, Subhadeep Kal, Carlos Fonseca, Xinghua Sun, Ryan Burns, Richard Farrell, David Hetzer, Andrew Metz, Akiteru Ko, Steven Scheer, Peter Biolsi, Anton DeVillers

Proceedings Volume 10147, 1014704 (2017) https://doi.org/10.1117/12.2258108

KEYWORDS: Optical lithography, Front end of line, Back end of line, Etching, Control systems, Semiconducting wafers, Logic, Extreme ultraviolet, TCAD, Computer simulations, Photomasks, Lithography, Metals

Read Abstract +

As the industry marches on onto the 5nm node and beyond, scaling has slowed down, with all major IDMs & foundries predicting a 3-4 year cadence for scaling. A major reason for this slowdown is not the technical challenge of making features smaller, but effective control of variation that creeps in to the fabrication process. That variability manifests itself as edge placement error (EPE), which has a direct impact on wafer yield. Simply defined as the variance between design intent vs. actual on-wafer results, EPE is one of the foremost challenges being faced by the industry at the advanced node for both logic and memory. This is especially critical at three stages: the front end of line (FEOL) STI patterning; middle of line (MOL) contact patterning; and back end of line (BEOL) trench patterning where the desired tight pitch demands EPE control beyond the capability of 193i multi-patterning or even EUV single pattern. In order to mitigate this EPE challenge, we are proposing self-alignment of blocks & cuts through a multi-color materials integration concept. This approach, termed as “Self-aligned block or Cut (SAB or SACut)”, simply trades off the un-manageable overlay requirement into a more manageable etch selectivity challenge, by having multiple materials filled in every other trench or line.

In this paper we will introduce self-alignment based block and cut strategies using multi-color materials integration and show implementation for BEOL trench block patterning. We will present a breakdown of the key unit process challenges that were needed to be resolved for enabling the self-alignment such as: (a) material selection of multi-color approach; (b) planarization of spin on materials; (c) void-free gap fill for high aspect ratio features; and last but not the least, (c) etch selectivity of etching one material with respect to all other materials exposed. Further, we will present a comparison of our new self-alignment approach with standard approaches where we will articulate the advantages in terms of EPE relaxation and mask number reduction. We will conclude our talk with a brief snapshot of the future direction of our EPE improvement strategies and our view on the future of patterning beyond 5nm node for the industry.

Proceedings Article | 7 April 2017 Presentation + Paper

Presentation + Paper

Self-aligned blocking integration demonstration for critical sub-40nm pitch Mx level patterning

Angélique Raley, Nihar Mohanty, Xinghua Sun, Richard Farrell, Jeffrey Smith, Akiteru Ko, Andrew Metz, Peter Biolsi, Anton Devilliers

Proceedings Volume 10149, 101490O (2017) https://doi.org/10.1117/12.2257769

KEYWORDS: Optical lithography, Photomasks, Metals, Etching, Double patterning technology, Overlay metrology, Semiconductors, Immersion lithography, Tolerancing, Optical alignment, Dielectrics, System on a chip, Plasma, Plasma etching, Lithography, Back end of line

Read Abstract +

Proceedings Article | 4 April 2017 Presentation + Paper

Presentation + Paper

Self-aligned quadruple patterning using spacer on spacer integration optimization for N5

Sophie Thibaut, Angélique Raley, Nihar Mohanty, Subhadeep Kal, Eric Liu, Akiteru Ko, David O'Meara, Kandabara Tapily, Peter Biolsi

Proceedings Volume 10149, 101490I (2017) https://doi.org/10.1117/12.2258173

KEYWORDS: Optical lithography, Double patterning technology, Etching, Error control coding, Semiconductors, Immersion lithography, Chemistry, Error analysis, Semiconducting wafers, Scanning electron microscopy, Line width roughness, Oxides, Spatial frequencies, Atomic layer deposition, Line edge roughness, Plasma

Read Abstract +

Proceedings Article | 24 March 2017 Presentation + Paper

Presentation + Paper

Ultrathin EUV patterning stack using polymer brush as an adhesion promotion layer

Indira Seshadri, Anuja De Silva, Luciana Meli, Charlie Liu, Cheng Chi, Jing Guo, Kristin Schmidt, Hoa Truang, John Arnold, Nelson Felix, Lovejeet Singh, Tsuyoshi Furukawa, Ramakrishnan Ayothi, Angelique Raley, Richard Farrell

Proceedings Volume 10143, 101431D (2017) https://doi.org/10.1117/12.2258565

KEYWORDS: Extreme ultraviolet, Optical lithography, Polymers, Etching, Extreme ultraviolet lithography, Photoresist materials, Lithography, Photoresist processing, Back end of line, Oxides, Head-mounted displays, Atomic layer deposition, Chemistry

Read Abstract +

Proceedings Article | 1 April 2016 Paper

Paper

Self-aligned quadruple patterning integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications

Angélique Raley, Sophie Thibaut, Nihar Mohanty, Kal Subhadeep, Satoru Nakamura, Akiteru Ko, David O'Meara, Kandabara Tapily, Steve Consiglio, Peter Biolsi

Proceedings Volume 9782, 97820F (2016) https://doi.org/10.1117/12.2219321

KEYWORDS: Titanium dioxide, Etching, Optical lithography, Silicon, Plasma, Silica, Atomic layer deposition, Line width roughness, Semiconducting wafers, Photoresist materials

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Proceedings Article | 17 March 2015 Paper

Paper

Challenges and mitigation strategies for resist trim etch in resist-mandrel based SAQP integration scheme

Nihar Mohanty, Elliott Franke, Eric Liu, Angelique Raley, Jeffrey Smith, Richard Farrell, Mingmei Wang, Kiyohito Ito, Sanjana Das, Akiteru Ko, Kaushik Kumar, Alok Ranjan, David O'Meara, Kenjiro Nawa, Steven Scheer, Anton DeVillers, Peter Biolsi

Proceedings Volume 9428, 94280G (2015) https://doi.org/10.1117/12.2085016

KEYWORDS: Etching, Optical lithography, Lithography, Plasma etching, Vacuum ultraviolet, Line edge roughness, Plasma, Semiconducting wafers, Line width roughness, Photomasks

Read Abstract +

Showing 5 of 24 publications

Conference Committee Involvement (4)

Advanced Etch Technology and Process Integration for Nanopatterning XIV

25 February 2025 | San Jose, California, United States

Advanced Etch Technology and Process Integration for Nanopatterning XIII

26 February 2024 | San Jose, California, United States

Advanced Etch Technology and Process Integration for Nanopatterning XII

28 February 2023 | San Jose, California, United States

Advanced Etch Technology and Process Integration for Nanopatterning XI

26 April 2022 | San Jose, California, United States

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