We propose a machine-learning-based mechanism to perform OPC, which is much more efficient than traditional OPC processes in terms of compute resources. Building a physical model for OPC takes a lot of labor and computational time, for example, model calibration requires thousands of cores for up to ten hours , and , OPC data prepare needs thousands of cores for a couple of days. We present a way to use learning to produce OPC mask designs from a large amount of lithography target data with a computationally cheap approach. Our technique uses learning based on pairs of lithography target data and OPCed mask. The impact of different learning algorithm on the quality and performance of mask prediction has been studied. We have tested multiple learning algorithm, such as PyTorch, Multilayer perceptron on IBM cloud. Preliminary evaluation of our technique on a standard contact EUV testsite shows accuracy similar to the standard processes using much less compute power.
Corner rounding improvement is critical to device performance, yield, and cell area reduction. In this paper, we present a method to use dual tone sub-resolution assist feature (SRAF) to improve both the outer corner rounding and inner corner rounding which in turn enhance the pattern quality. The simulation data and wafer data are presented. A few parameters have been investigated, such as the position of the SRAF, the shape of the SRAF, resist type and mask tone. The preliminary results show that more than 40% reduction of both inner corner rounding and outer corner rounding can be achieved by placing sub-resolution assist features at appropriate locations. The limit of corner rounding improvement is determined by mask rule check (MRC) and resist sensitivities.
Lithographic and pitch-multiplying spacer technologies are widely used to shrink interconnect periodicity within critical layers. This places significant burden on overlay and CD uniformity of the subsequently patterned vias to physically contact and electrically connect critical layers to the rest of the integrated circuit in a nearly defect-free and perfectly-consistent manner. We are evaluating the combination of EUV and DSA patterning technologies to meet this challenge and enable future technology nodes. The contact hole guide pattern is fabricated atop bilayer hardmask material by single-exposure EUV, surface-modified with telechelic polymer brush materials, and finally shrunk/rectified using self-assembled, lamella-forming polystyrene-block-polymethylmethacrylate (PS-b-PMMA). The nascent via pattern is then blanket exposed by DUV light and the photolyzed PMMA is selectively rinsed away. Here we study the process performance of DSA pattern wet etch chemistry and subsequent dry etch pattern transfer into bilayer hardmask material using both metrology and electrical yield measurements as evaluation criteria. In particular, the choice of wet etch solvation strength selective towards PMMA was varied from moderate (isopropanol, IPA) to good (acetic acid, AAc). Due to the ability of AAC to solubilize all covalently-untethered PMMA, regardless of molecular weight, the resulting average CD is wider and its local distribution is more uniform. In contrast, IPA is only capable of rinsing away the smallest PMMA fragments, resulting in relatively tighter bounds about the preferable blanket UV dose, and a smaller average CD and less-uniform local CD distribution. These morphological differences are confirmed by cross-sectional transmission electron micrographs. Brightfield inspection and inline electrical testing are used to compare relative defectivity and yield, respectively, to assess the potential impact on device performance for processes utilizing either solvent.
This paper presents a design and technology co-optimization (DTCO) study of metal cut formation in the sub-20-nmregime. We propose to form the cuts by applying grapho-epitaxial directed self-assembly. The construction of a DTCO flow is explained and results of a process variation analysis are presented. We examined two different DSA models and evaluated their performance and speed tradeoff. The applicability of each model type in DTCO is discussed and categorized.
KEYWORDS: Etching, Critical dimension metrology, Metals, Directed self assembly, Oxides, Back end of line, Dielectrics, Scanning electron microscopy, Tin, Lithography
The progress of using DSA for metal cut to achieve sub-20nm tip-to-tip (t2t) critical dimension (CD) is reported. Small and uniform t2t CD is very challenging due to lithographic limitation but holds the key to backend-of-the-line (BEOL) scaling. An integration scheme is demonstrated that allows the combination of design flexibility and fine, rectified local CD uniformity (LCDU). The combined effect of LCDU and centroid jittering will be discussed and compared to a hole shrink process using atomic layer deposition and spacer formation. The learning from this case study can provide perspectives that may not have been investigated thoroughly in the past. By including more important elements during DSA process development, such as metal cut, the DSA maturit y can be further advanced and move DSA closer to HVM adoption.
Initial readiness of extreme ultraviolet (EUV) patterning has been demonstrated at the 7-nm device node with the focus now shifting to driving the “effective” k1 factor and enabling the second generation of EUV patterning. In current EUV lithography, photoresist thicknesses <30 nm are required to meet resolution targets and mitigate pattern collapse. Etch budgets necessitate the reduction of underlayer thickness as well. Typical spin-on underlayers show high defectivity when reducing thickness to match thinner resist. Inorganic deposited underlayers are lower in defectivity and can potentially enable ultrathin EUV patterning stacks. However, poor resist-inorganic underlayer adhesion severely limits their use. Existing adhesion promotion techniques are found to be either ineffective or negatively affect the etch budget. Using a grafted polymer brush adhesion layer, we demonstrate an ultrathin EUV patterning stack comprised of inorganic underlayer, polymer brush, and resist. We show printing of sub-36-nm pitch features with a good lithography process window and low defectivity on various inorganic substrates, with significant improvement over existing adhesion promotion techniques. We systematically study the effect of brush composition, molecular weight, and deposition time/temperature to optimize grafting and adhesion. We also show process feasibility and extendibility through pattern transfer from the resist into typical back end stacks.
KEYWORDS: 3D modeling, Calibration, Data modeling, Optical lithography, Nanotechnology, Very large scale integration, System on a chip, Logic, Research facilities
Direct Optimization (DO) of a 3D DSA model is a more optimal approach to a DTCO study in terms of accuracy and speed compared to a Cahn Hilliard Equation solver. DO’s shorter run time (10X to 100X faster) and linear scaling makes it scalable to the area required for a DTCO study. However, the lack of temporal data output, as opposed to prior art, requires a new calibration method. The new method involves a specific set of calibration patterns. The calibration pattern’s design is extremely important when temporal data is absent to obtain robust model parameters. A model calibrated to a Hybrid DSA system with a set of device-relevant constructs indicates the effectiveness of using nontemporal data. Preliminary model prediction using programmed defects on chemo-epitaxy shows encouraging results and agree qualitatively well with theoretical predictions from a strong segregation theory.
In this study, the integrity and the benefits of the DSA shrink process were verified through a via-chain test structure, which was fabricated by either DSA or baseline litho/etch process for via layer formation while metal layer processes remain the same. The nearest distance between the vias in this test structure is below 60nm, therefore, the following process components were included: 1) lamella-forming BCP for forming self-aligned via (SAV), 2) EUV printed guiding pattern, and 3) PS-philic sidewall. The local CDU (LCDU) of minor axis was improved by 30% after DSA shrink process. We compared two DSA Via shrink processes and a DSA_Control process, in which guiding patterns (GP) were directly transferred to the bottom OPL without DSA shrink. The DSA_Control apparently resulted in larger CD, thus, showed much higher open current and shorted the dense via chains. The non-optimized DSA shrink process showed much broader current distribution than the improved DSA shrink process, which we attributed to distortion and dislocation of the vias and ineffective SAV. Furthermore, preliminary defectivity study of our latest DSA process showed that the primary defect mode is likely to be etch-related. The challenges, strategies applied to improve local CD uniformity and electrical current distribution, and potential adjustments were also discussed.
The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.
Initial readiness of EUV patterning has been demonstrated at the 7-nm device node with the focus now shifting to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. In current EUV lithography, photoresist thicknesses <30 nm are required to meet resolution targets and mitigate pattern collapse. Etch budgets necessitate the reduction of underlayer thickness as well. Typical spin-on underlayers show high defectivity when reducing thickness to match thinner resist. Inorganic deposited underlayers are lower in defectivity and can potentially enable ultrathin EUV patterning stacks. However, poor resist-inorganic underlayer adhesion severely limits their use. Existing adhesion promotion techniques are found to be either ineffective or negatively affect the etch budget. Here, using a grafted polymer brush adhesion layer we demonstrate an ultrathin EUV patterning stack comprised of inorganic underlayer, polymer brush and resist. We show printing of sub-36 nm pitch features with good lithography process window and low defectivity on various inorganic substrates, with significant improvement over existing adhesion promotion techniques. We systematically study the effect of brush composition, molecular weight and deposition time/temperature to optimize grafting and adhesion. We also show process feasibility and extendibility through pattern transfer from the resist into typical back end stacks.
We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing.
Directed self-assembly (DSA) of block copolymers (BCPs) has become a promising patterning technique for 7nm node hole shrink process due to its material-controlled CD uniformity and process simplicity.[1] For such application, cylinder-forming BCP system has been extensively investigated compared to its counterpart, lamella-forming system, mainly because cylindrical BCPs will form multiple vias in non-circular guiding patterns (GPs), which is considered to be closer to technological needs.[2-5] This technological need to generate multiple DSA domains in a bar-shape GP originated from the resolution limit of lithography, i.e. those vias placed too close to each other will merge and short the circuit. In practice, multiple patterning and self-aligned via (SAV) processes have been implemented in semiconductor manufacturing to address this resolution issue.[6] The former approach separates one pattern layer with unresolvable dense features into several layers with resolvable features, while the latter approach simply utilizes the superposition of via bars and the pre-defined metal trench patterns in a thin hard mask layer to resolve individual vias, as illustrated in Fig 1 (upper). With proper design, using DSA to generate via bars with the SAV process could provide another approach to address the resolution issue.
In recent years major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCP). DSA is now widely regarded as a leading complementary patterning technique for future node integrated circuit (IC) device manufacturing and is considered for the 7 nm node. One of the most straightforward approaches for implementation of DSA is via patterning by graphoepitaxy. In this approach, the guiding pattern dictates the location and pitch of the resulting hole structures while the material properties of the BCP control the feature size and uniformity. Tight pitches need to be available for a successful implementation of DSA for future node via patterning which requires DSA in small guiding pattern CDs. Here, we show strategies how to enable the desired CD shrink in these small guiding pattern vias by utilizing high χ block copolymers and/or controlling the surface properties of the template, i.e. sidewall and bottom affinity to the blocks.
We have performed a systematic study regarding the diblock composition to keep the size of the cylinders relatively constant despite the shape of the guiding pattern. We have also explored how some guiding patterns shapes provide acceptable cylindrical assembly using an EUV exposure system. This study assumes that LER is a random phenomenon which conformably follows the shape of the guiding pattern. While the edges of the guiding pattern have fluctuations related to the LER of the EUV resist, as long as the centroid of the guiding pattern remains constant, the rectification characteristics of DSA permits adequate hole formation. In this paper we include the level of LER a guiding pattern can exhibit given a pre-determined diblock copolymer / homopolymer mixture. As the amount of homopolymer increases, the size and placement of the assembled diblock becomes less sensitive to the guiding pattern’s edge roughness. This study also explores how the addition of homopolymer is only effective up to a point, as a homopolymer-rich blend is not able to assemble properly. One of the concerns about homopolymer-rich mixtures is the effect it has in the formation of defects. Such effect has not been fully characterized but this study serves as the basis for testing optimal combinations of materials and lithography settings for an EUV system, with the end goal to enable contact/via printing at lower EUV source power requirements.
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