Dr. Michael C. Smayling Profile

Dr. Michael C. Smayling

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Publications (38)

Proceedings Article | 22 March 2016 Open Access

Lithography alternatives meet design style reality: How do they "line" up?

Michael Smayling

Proceedings Volume 9777, 977702 (2016) https://doi.org/10.1117/12.2224685

KEYWORDS: Directed self assembly, Lithography, Optical lithography, Source mask optimization, Optical resolution, Logic, Electron beam lithography, Transistors, Electronics, Photomasks, Optics manufacturing

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Optical lithography resolution scaling has stalled, giving innovative alternatives a window of opportunity. One important factor that impacts these lithographic approaches is the transition in design style from 2D to 1D for advanced CMOS logic. Just as the transition from 3D circuits to 2D fabrication 50 years ago created an opportunity for a new breed of electronics companies, the transition today presents exciting and challenging time for lithographers. Today, we are looking at a range of non-optical lithography processes. Those considered here can be broadly categorized: self-aligned lithography, self-assembled lithography, deposition lithography, nano-imprint lithography, pixelated e-beam lithography, shot-based e-beam lithography .Do any of these alternatives benefit from or take advantage of 1D layout? Yes, for example SAPD + CL (Self Aligned Pitch Division combined with Complementary Lithography). This is a widely adopted process for CMOS nodes at 22nm and below. Can there be additional design / process co-optimization? In spite of the simple-looking nature of 1D layout, the placement of “cut” in the lines and “holes” for interlayer connections can be tuned for a given process capability. Examples of such optimization have been presented at this conference, typically showing a reduction of at least one in the number of cut or hole patterns needed.[1,2] Can any of the alternatives complement each other or optical lithography? Yes.[3] For example, DSA (Directed Self Assembly) combines optical lithography with self-assembly. CEBL (Complementary e-Beam Lithography) combines optical lithography with SAPD for lines with shot-based e-beam lithography for cuts and holes. Does one (shrinking) size fit all? No, that’s why we have many alternatives. For example NIL (Nano-imprint Lithography) has been introduced for NAND Flash patterning where the (trending lower) defectivity is acceptable for the product. Deposition lithography has been introduced in 3D NAND Flash to set the channel length of select and memory transistors.

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Proceedings Article | 9 July 2015 Paper

Pitch-based pattern splitting for 1D layout

Ryo Nakayama, Hiroyuki Ishii, Koji Mikami, Koichiro Tsujita, Hidetami Yaegashi, Kenichi Oyama, Michael Smayling, Valery Axelrad

Proceedings Volume 9658, 96580A (2015) https://doi.org/10.1117/12.2192529

KEYWORDS: Optical lithography, Photomasks, Source mask optimization, Lithography, Etching, Scanning electron microscopy, Logic devices, Computer programming, Photovoltaics, Metals

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Proceedings Article | 18 March 2015 Paper

7nm logic optical lithography with OPC-Lite

Michael Smayling, Koichiro Tsujita, Hidetami Yaegashi, Valery Axelrad, Ryo Nakayama, Kenichi Oyama, Shohei Yamauchi, Hiroyuki Ishii, Koji Mikami

Proceedings Volume 9426, 94261U (2015) https://doi.org/10.1117/12.2084846

KEYWORDS: Optical lithography, Logic, Double patterning technology, Etching, Optical proximity correction, Photomasks, Source mask optimization, Neodymium, Fiber optic illuminators, Picosecond phenomena

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The CMOS logic 22nm node was the last one done with single patterning. It used a highly regular layout style with Gridded Design Rules (GDR). Smaller nodes have required the same regular layout style but with multiple patterning for critical layers. A “line/cut” approach is being used to achieve good pattern fidelity and process margin.[1] As shown in Fig. 1, even with “line” patterns, pitch division will eventually be necessary.

For the “cut” pattern, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective at the 20nm node and below.[2,3,4] Single patterning was found to be suitable down to 16nm, while double patterning extended optical lithography for cuts to the 10-12nm nodes. Design optimization avoided the need for triple patterning. Lines can be patterned with 193nm immersion with no complex OPC. The final line dimensions can be achieved by applying pitch division by two or four.[5]

In this study, we extend the scaling using simplified OPC to the 7nm node for critical FEOL and BEOL layers. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops, scaled from previous experiments.

Simulation results show that for cuts at 7nm logic dimensions, the gate layer can be done with single patterning whose minimum pitch is 53nm, possibly some of the 1x metal layers can be done with double patterning whose minimum pitch is 53nm, and the contact layer will require triple patterning whose minimum pitch is 68nm. These pitches are less than the resolution limit of ArF NA=1.35 (72nm). However these patterns can be separated by a combination of innovative SMO for less than optical resolution limit and a process trick of hole-repair technique. An example of triple patterning coloring is shown in Fig 3. Fin and local interconnect are created by lines and trims. The number of trim patterns are 3 times (min. pitch=90nm) and twice (min. pitch=120nm), respectively. The small number of masks, large pitches, and simple patterns of trims come from the simple 1D layout design.

Experimental demonstration of these cut layers using design optimization, OPC-Lite, and conventional illuminators at the 7nm node dimensions will be presented. Lines were patterned with 193nm immersion with no complex OPC. The final line dimensions (22nm pitch) were achieved with pitch division 4.[5]

Proceedings Article | 16 September 2014 Paper

OPC-Lite for gridded designs at low k1

V. Axelrad, M. Smayling, K. Tsujita, K. Mikami, H. Yaegashi

Proceedings Volume 9235, 92350C (2014) https://doi.org/10.1117/12.2069353

KEYWORDS: Optical proximity correction, Lithography, Double patterning technology, Critical dimension metrology, Manufacturing, Photomasks, Optics manufacturing, Scanning electron microscopy, Databases, Image processing

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Proceedings Article | 31 March 2014 Paper

Characterization of 1D layout technology at advanced nodes and low k1

V. Axelrad, K. Mikami, M. Smayling, K. Tsujita, H. Yaegashi

Proceedings Volume 9052, 905213 (2014) https://doi.org/10.1117/12.2046120

KEYWORDS: Field effect transistors, Optical lithography, Lithography, Manufacturing, Double patterning technology, Device simulation, Photomasks, Calibration, Image processing, Photovoltaics

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Proceedings Article | 31 March 2014 Paper

11nm logic lithography with OPC-lite

Michael Smayling, Koichiro Tsujita, Hidetami Yaegashi, Valery Axelrad, Ryo Nakayama, Kenichi Oyama, Arisa Hara

Proceedings Volume 9052, 90520M (2014) https://doi.org/10.1117/12.2045667

KEYWORDS: Logic, Photomasks, Semiconducting wafers, Optical proximity correction, Source mask optimization, Fiber optic illuminators, Lithography, Double patterning technology, Etching, Convolution

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Proceedings Article | 9 September 2013 Paper

1D design style implications for mask making and CEBL

Michael Smayling

Proceedings Volume 8880, 888012 (2013) https://doi.org/10.1117/12.2030684

KEYWORDS: Photomasks, Optical proximity correction, Electron beam lithography, Mask making, Semiconducting wafers, Logic, Optical lithography, Line edge roughness, Lithography, Electron beam direct write lithography

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At advanced nodes, CMOS logic is being designed in a highly regular design style because of the resolution limitations of optical lithography equipment. Logic and memory layouts using 1D Gridded Design Rules (GDR) have been demonstrated to nodes beyond 12nm.[1-4] Smaller nodes will require the same regular layout style but with multiple patterning for critical layers. One of the significant advantages of 1D GDR is the ease of splitting layouts into lines and cuts. A lines and cuts approach has been used to achieve good pattern fidelity and process margin to below 12nm.[4] Line scaling with excellent line-edge roughness (LER) has been demonstrated with self-aligned spacer processing.[5] This change in design style has important implications for mask making: • The complexity of the masks will be greatly reduced from what would be required for 2D designs with very complex OPC or inverse lithography corrections. • The number of masks will initially increase, as for conventional multiple patterning. But in the case of 1D design, there are future options for mask count reduction. • The line masks will remain simple, with little or no OPC, at pitches (1x) above 80nm. This provides an excellent opportunity for continual improvement of line CD and LER. The line pattern will be processed through a self-aligned pitch division sequence to divide pitch by 2 or by 4. • The cut masks can be done with “simple OPC” as demonstrated to beyond 12nm.[6] Multiple simple cut masks may be required at advanced nodes. “Coloring” has been demonstrated to below 12nm for two colors and to 8nm for three colors. • Cut/hole masks will eventually be replaced by e-beam direct write using complementary e-beam lithography (CEBL).[7-11] This transition is gated by the availability of multiple column e-beam systems with throughput adequate for high- volume manufacturing. A brief description of 1D and 2D design styles will be presented, followed by examples of 1D layouts. Mask complexity for 1D layouts patterned directly will be compared to mask complexity for lines and cuts at nodes larger than 20nm. No such comparison is possible below 20nm since single-patterning does not work below ~80nm pitch using optical exposure tools. Also discussed will be recently published wafer results for line patterns with pitch division by-2 and by-4 at sub-12nm nodes, plus examples of post-etch results for 1D patterns done with cut masks and compared to cuts exposed by a single-column e-beam direct write system.

Proceedings Article | 12 April 2013 Paper

Sub-12nm optical lithography with 4x pitch division and SMO-lite

Michael Smayling, Koichiro Tsujita, Hidetami Yaegashi, Valery Axelrad, Tadashi Arai, Kenichi Oyama, Arisa Hara

Proceedings Volume 8683, 868305 (2013) https://doi.org/10.1117/12.2011329

KEYWORDS: Optical lithography, Photomasks, Logic, Optical proximity correction, Double patterning technology, Semiconducting wafers, Transmission electron microscopy, Source mask optimization, Neodymium, Etching

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Proceedings Article | 8 November 2012 Paper

Improvement of lithographic performance and reduction of mask cost by simple OPC

Koichiro Tsujita, Koji Mikami, Hiroyuki Ishii, Tadashi Arai, Ryo Nakayama, Michael Smayling, Valery Axelrad, Hidetami Yaegashi, Kenichi Oyama

Proceedings Volume 8522, 852209 (2012) https://doi.org/10.1117/12.961118

KEYWORDS: Photomasks, Optical proximity correction, Source mask optimization, Metals, Lithography, Photovoltaics, Semiconducting wafers, Scanning electron microscopy, SRAF, Inspection

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Proceedings Article | 21 March 2012 Paper

Sub-20nm hybrid lithography using optical, pitch-division, and e-beam

J. Belledent, M. Smayling, J. Pradelles, P. Pimenta-Barros, S. Barnola, L. Mage, B. Icard, C. Lapeyre, S. Soulan, L. Pain

Proceedings Volume 8323, 83230F (2012) https://doi.org/10.1117/12.916486

KEYWORDS: Electron beam lithography, Photomasks, Lithography, Optical lithography, Logic, Optics manufacturing, Semiconducting wafers, Double patterning technology, Neodymium, Scanning electron microscopy

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A roadmap extending far beyond the current 22nm CMOS node has been presented several times. [1] This roadmap includes the use of a highly regular layout style which can be decomposed into "lines and cuts."[2] The "lines" can be done with existing optical immersion lithography and pitch division with self-aligned spacers.[3] The "cuts" can be done with either multiple exposures using immersion lithography, or a hybrid solution using either EUV or direct-write ebeam.[ 4] The choice for "cuts" will be driven by the availability of cost-effective, manufacturing-ready equipment and infrastructure. Optical lithography improvements have enabled scaling far beyond what was expected; for example, soft x-rays (aka EUV) were in the semiconductor roadmap as early as 1994 since optical resolution was not expected for sub-100nm features. However, steady improvements and innovations such as Excimer laser sources and immersion photolithography have allowed some manufacturers to build 22nm CMOS SOCs with single-exposure optical lithography. With the transition from random complex 2D shapes to regular 1D-patterns at 28nm, the "lines and cuts" approach can extend CMOS logic to at least the 7nm node. The spacer double patterning for lines and optical cuts patterning is expected to be used down to the 14nm node. In this study, we extend the scaling to 18nm half-pitch which is approximately the 10-11nm node using spacer pitch division and complementary e-beam lithography. For practical reasons, E-Beam lithography is used as well to expose the "mandrel" patterns that support the spacers. However, in a production mode, it might be cost effective to replace this step by a standard 193nm exposure and applying the spacer technique twice to divide the pitch by 3 or 4. The Metal-1 "cut" pattern is designed for a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Since the final conductor is defined by a Damascene process, the "cut" patterns become islands of resist blocking hard-mask trenches. The shapes are often small and positioned on a dense grid making this layer to be the most critical one. This is why direct-write e-beam patterning, possibly using massively parallel beams, is well suited for this task. In this study, we show that a conventional shaped beam system can already pattern the 11nm node Metal-1 layer with reasonable overlay margin. The combination of design style, optical lithography plus pitch-division, and e-beam lithography appears to provide a scaling path far into the future.

Proceedings Article | 13 March 2012 Paper

Sub-20nm logic lithography optimization with simple OPC and multiple pitch division

Michael Smayling, Valery Axelrad, Koichiro Tsujita, Hidetami Yaegashi, Ryo Nakayama, Kenichi Oyama, Yuichi Gyoda

Proceedings Volume 8326, 832613 (2012) https://doi.org/10.1117/12.914916

KEYWORDS: Optical proximity correction, Logic, Photomasks, Optical lithography, Etching, Lithography, Acquisition tracking and pointing, Photovoltaics, Semiconducting wafers, Scanning electron microscopy

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Proceedings Article | 4 April 2011 Paper

E-beam to complement optical lithography for 1D layouts

David Lam, Enden Liu, Michael Smayling, Ted Prescop

Proceedings Volume 7970, 797011 (2011) https://doi.org/10.1117/12.879479

KEYWORDS: Electron beam lithography, Lithography, Optical lithography, Semiconducting wafers, Photomasks, Logic, 193nm lithography, Optical alignment, Semiconductors, Metals

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Proceedings Article | 23 March 2011 Paper

Supreme lithographic performance by simple mask layout based on lithography and layout co-optimization

Koichiro Tsujita, Tadashi Arai, Hiroyuki Ishii, Yuichi Gyoda, Kazuhiro Takahashi, Valery Axelrad, Michael Smayling

Proceedings Volume 7973, 79730D (2011) https://doi.org/10.1117/12.878663

KEYWORDS: Photomasks, Lithography, Optical proximity correction, SRAF, Lithographic illumination, Source mask optimization, Binary data, Double patterning technology, Computer programming, Nanoimprint lithography

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Proceedings Article | 23 March 2011 Paper

Custom source and mask optimization for 20nm SRAM and logic

Michael Smayling, Tamer Coskun, Vishnu Kamat

Proceedings Volume 7973, 79731W (2011) https://doi.org/10.1117/12.881662

KEYWORDS: Logic, Source mask optimization, Fiber optic illuminators, Optical lithography, Photomasks, Double patterning technology, Metals, Lithography, Nanoimprint lithography, System on a chip

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Proceedings Article | 23 March 2011 Paper

Joint optimization of layout and litho for SRAM and logic towards the 20nm node using 193i

Peter De Bisschop, Bart Laenens, Kazuya Iwase, Teruyoshi Yao, Mircea Dusa, Michael Smayling

Proceedings Volume 7973, 79730B (2011) https://doi.org/10.1117/12.881688

KEYWORDS: Logic, Lithium, Source mask optimization, Optical lithography, Double patterning technology, Surface plasmons, Transistors, Photovoltaics, Photomasks, Semiconducting wafers

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Proceedings Article | 23 March 2011 Paper

Optical lithography applied to 20-nm CMOS Logic and SRAM

V. Axelrad, M. Smayling, K. Tsujita, K. Takahashi

Proceedings Volume 7973, 797314 (2011) https://doi.org/10.1117/12.879522

KEYWORDS: Logic, Scanners, Source mask optimization, Optical lithography, Lithography, Transistors, 193nm lithography, Lithographic illumination, Cadmium, Double patterning technology

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Proceedings Article | 3 April 2010 Paper

16nm with 193nm immersion lithography and double exposure

Valery Axelrad, Michael Smayling

Proceedings Volume 7641, 764109 (2010) https://doi.org/10.1117/12.846677

KEYWORDS: Scanners, Lithography, Lithium, Image quality, Manufacturing, Immersion lithography, Lithographic illumination, Double patterning technology, 193nm lithography, Optical proximity correction

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Proceedings Article | 11 March 2010 Paper

Joint-optimization for SRAM and logic for 28nm node and below

Staf Verhaegen, Michael Smayling, Peter De Bisschop, Bart Laenens

Proceedings Volume 7641, 764107 (2010) https://doi.org/10.1117/12.846595

KEYWORDS: Logic, Lithography, Optical lithography, Double patterning technology, Electroluminescence, Fiber optic illuminators, Transistors, Photomasks, Source mask optimization, Lithium

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Proceedings Article | 4 March 2010 Paper

Interlayer self-aligning process for 22nm logic

Michael Smayling, Stewart Robertson, Damian Lacey, Sanjay Kapasi

Proceedings Volume 7640, 76401V (2010) https://doi.org/10.1117/12.846562

KEYWORDS: Logic, Semiconducting wafers, Aluminum, Photomasks, Photoresist materials, Optical alignment, Optical lithography, Scanning electron microscopy, Metals, Diffusion

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Proceedings Article | 4 March 2010 Paper

22nm logic lithography in the presence of local interconnect

Michael Smayling, Robert Socha, Mircea Dusa

Proceedings Volume 7640, 764019 (2010) https://doi.org/10.1117/12.846580

KEYWORDS: Photomasks, Metals, Lithography, Optical lithography, Logic, Source mask optimization, Photovoltaics, Optical proximity correction, Lithium, SRAF

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The 22nm logic node is being approached from at least two different scaling paths. One approach "B" will use Gate and 1x Metal pitches of approximately 80nm, which, combined with the appropriate design style, may allow single exposure to be used. The other combination under consideration "A" will have a Gate pitch of ~90nm and a 1x Metal pitch of 70nm. Even with immersion scanners, the Rayleigh k1 factor is below 0.32 for 90nm pitch and below the single exposure resolution limits when the pitch is below 80nm. Although highly regular gridded patterns help [1,2,3], one of the critical issues for 22nm patterning is Contact and Via patterning. The lines / cuts approach works well for the poly and interconnect layers, but the "hole" layers have less benefit from gridded designs and remain a big challenge for patterning. One approach to reduce the lithography optimization problem is to reconsider the interconnection stack. The Contact layer is complex because it is connecting two layers on the bottom - Active and Gate - to one layer on the top. Other layers such as Via-1 only have one layer on the bottom. A potential solution is a Local Interconnect layer. This layer could be formed as part of the salicide process module, where a patterned etch would replace the blanket strip of un-reacted metal of the silicide layer. Local interconnect lines would run parallel to the Gate electrodes, eliminating "wrong-way" lines in the Active layer. Depending on the final pitch chosen, Local Interconnect could be single or double patterned, or could be done with a self-aligned process plus a cut mask. Example layouts of standard cells have shown a significant benefit with local interconnects. For example, the Contact count is reduced by ~25%, and in many cases Via-1 and Metal-2 usage was eliminated. The simplified Active pattern, along with reduced contact count and density, permit a different lithography optimization for the cells designed with Local Interconnect. Metal-1 complexity was also reduced. Details of lithography optimization results for critical layers, Active, Gate, Local Interconnect, Contact, and Metal-1 will be presented.

Proceedings Article | 18 March 2009 Paper

Interference assisted lithography for patterning of 1D gridded design

Robert Greenway, Rudolf Hendel, Kwangok Jeong, Andrew Kahng, John Petersen, Zhilong Rao, Michael Smayling

Proceedings Volume 7271, 72712U (2009) https://doi.org/10.1117/12.812033

KEYWORDS: Lithography, Diffusion, Photomasks, Critical dimension metrology, Optical lithography, 193nm lithography, Double patterning technology, Logic, Metals, Electron beam lithography

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Proceedings Article | 16 March 2009 Paper

32nm and below logic patterning using optimized illumination and double patterning

Michael Smayling, Valery Axelrad

Proceedings Volume 7274, 72740K (2009) https://doi.org/10.1117/12.814258

KEYWORDS: Logic, Optical lithography, Double patterning technology, Fiber optic illuminators, Lithography, Photomasks, Optical proximity correction, Nanoimprint lithography, Diffusion, Photoresist materials

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Proceedings Article | 12 March 2008 Paper

Low-k1 logic design using gridded design rules

Michael Smayling, Hua-yu Liu, Lynn Cai

Proceedings Volume 6925, 69250B (2008) https://doi.org/10.1117/12.772875

KEYWORDS: Logic, Optical proximity correction, Critical dimension metrology, Scanners, Semiconducting wafers, Optical lithography, Etching, Photomasks, Resolution enhancement technologies, Fiber optic illuminators

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Proceedings Article | 4 March 2008 Paper

APF pitch-halving for 22nm logic cells using gridded design rules

Michael Smayling, Christopher Bencher, Hao Chen, Huixiong Dai, Michael Duane

Proceedings Volume 6925, 69251E (2008) https://doi.org/10.1117/12.772905

KEYWORDS: Logic, Photomasks, Optical lithography, Etching, Transistors, Double patterning technology, Chemical vapor deposition, Semiconducting wafers, Dielectrics, Image processing

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Proceedings Article | 28 December 2007 Paper

SoC variability evaluation and reduction

Artur Balasinski, Michael Smayling, Valery Axelrad

Proceedings Volume 6798, 67980I (2007) https://doi.org/10.1117/12.758782

KEYWORDS: Computer aided design, Optical proximity correction, Design for manufacturing, Manufacturing, System on a chip, Field effect transistors, Calibration, Etching, Lithography, Analog electronics

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Proceedings Article | 6 December 2004 Paper

Accelerating yield ramp through design and manufacturing collaboration

Robin Sarma, Huixiong Dai, Michael Smayling, Michael Duane

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.572591

KEYWORDS: Photomasks, Semiconducting wafers, Manufacturing, Design for manufacturability, Reticles, Vestigial sideband modulation, Diagnostics, Failure analysis, Optical proximity correction, Resolution enhancement technologies

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Proceedings Article | 3 May 2004 Paper

Manufacturability of the X Architecture at the 90-nm technology node

Michael Smayling, Robin Sarma, Toshiyuki Nagata, Narain Arora, Michael Duane, Shiany Oemardani, Santosh Shah

Proceedings Volume 5379, (2004) https://doi.org/10.1117/12.536027

KEYWORDS: Optical proximity correction, Resistance, Manufacturing, Semiconducting wafers, Resistors, Metals, Lithography, Scanners, Metrology, Photomasks

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Proceedings Article | 3 May 2004 Paper

Taking the X Architecture to the 65-nm technology node

Robin Sarma, Michael Smayling, Narain Arora, Toshiyuki Nagata, Michael Duane, Santosh Shah, Harris Keston, Shiany Oemardani

Proceedings Volume 5379, (2004) https://doi.org/10.1117/12.536130

KEYWORDS: Photomasks, Manufacturing, Metals, Semiconducting wafers, Critical dimension metrology, Optical proximity correction, Resistance, Lithography, Dielectrics, Copper

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Proceedings Article | 26 July 1999 Paper

Coherent multiple imaging by means of pupil plane filtering

Miklos Erdelyi, Armen Kroyan, Karoly Osvay, Zsolt Bor, William Wilson, Michael Smayling, Frank Tittel

Proceedings Volume 3679, (1999) https://doi.org/10.1117/12.354393

KEYWORDS: Fabry–Perot interferometers, Image filtering, Coherence imaging, Optical filters, Photomasks, Resolution enhancement technologies, Spatial coherence, Image enhancement, Phase shifts, Image resolution

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Proceedings Article | 28 April 1999 Paper

Enhanced microlithography using coherent multiple imaging

Miklos Erdelyi, Karoly Osvay, Zsolt Bor, William Wilson, Michael Smayling, Frank Tittel

Proceedings Volume 3741, (1999) https://doi.org/10.1117/12.346891

KEYWORDS: Fabry–Perot interferometers, Diffraction, Photomasks, Image filtering, Coherence imaging, Optical filters, Optical lithography, Image processing, Mirrors, Image quality

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Proceedings Article | 29 June 1998 Paper

Present and future trends in excimer-laser-based microlithography

Frank Tittel, Miklos Erdelyi, Zoltan Horvath, Armen Kroyan, William Wilson, Michael Smayling, Zsolt Bor, Gabor Szabo

Proceedings Volume 3403, (1998) https://doi.org/10.1117/12.311947

KEYWORDS: Fabry–Perot interferometers, Objectives, Optical lithography, Wafer-level optics, Excimer lasers, Resolution enhancement technologies, Semiconducting wafers, Integrated optics, Microscopes, Mirrors

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Proceedings Article | 7 July 1997 Paper

Optical microlithography with nearly nondiffracting beams

Miklos Erdelyi, Zoltan Horvath, Zsolt Bor, Gabor Szabo, Joseph Cavallaro, Michael Smayling, Frank Tittel

Proceedings Volume 3051, (1997) https://doi.org/10.1117/12.276053

KEYWORDS: Optical lithography, Nondiffracting beams, Fabry–Perot interferometry, Bessel beams, Image resolution, Diffraction, Phase shifting

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Proceedings Article | 4 April 1997 Paper

High resolution microlithography applications of deep-UV excimer lasers

Frank Tittel, Joseph Cavallaro, Miklos Erdelyi, Gabor Szabo, Zsolt Bor, Michael Smayling

Proceedings Volume 3092, (1997) https://doi.org/10.1117/12.270108

KEYWORDS: Optical lithography, Deep ultraviolet, Objectives, Excimer lasers, Fabry–Perot interferometers, Mirrors, Bessel beams, Fabry–Perot interferometry, Image resolution, Interferometers

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Proceedings Article | 7 June 1996 Paper

Integrated CAD framework linking VLSI layout editors and process simulators

Chaitali Sengupta, Miklos Erdelyi, Zsolt Bor, Joseph Cavallaro, Michael Smayling, Gabor Szabo, Frank Tittel, William Wilson

Proceedings Volume 2726, (1996) https://doi.org/10.1117/12.240955

KEYWORDS: Computer aided design, Phase shifts, Photomasks, Phase shifting, Binary data, Very large scale integration, Lithographic illumination, Photoresist materials, Interferometry, Silicon

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Proceedings Article | 7 June 1996 Paper

Sub-quarter-micrometer contact hole fabrication using annular illumination

Miklos Erdelyi, Zsolt Bor, Gabor Szabo, Joseph Cavallaro, Michael Smayling, Frank Tittel, William Wilson

Proceedings Volume 2726, (1996) https://doi.org/10.1117/12.240953

KEYWORDS: Photoresist materials, Imaging systems, Diffraction, Spatial filters, Spectral resolution, Fabrication, Excimer lasers, Silica, Optical lithography, Resolution enhancement technologies

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Proceedings Article | 26 May 1995 Paper

New interferometric phase-shifting technique for sub-half-micron laser microlithography

Miklos Erdelyi, Chaitali Sengupta, Zsolt Bor, Joseph Cavallaro, Motoi Kido, Michael Smayling, Frank Tittel, William Wilson, Gabor Szabo

Proceedings Volume 2440, (1995) https://doi.org/10.1117/12.209308

KEYWORDS: Computer aided design, Phase shifting, Photomasks, Interferometry, Phase shifts, Photoresist materials, Optical lithography, Lithography, Semiconducting wafers, Binary data

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Proceedings Article | 17 April 1995 Paper

New phase-shifting technique for deep UV excimer laser-based lithography

Zsolt Bor, Joseph Cavallaro, Miklos Erdelyi, Motoi Kido, Chaitali Sengupta, Michael Smayling, Gabor Szabo, Frank Tittel, William Wilson

Proceedings Volume 2380, (1995) https://doi.org/10.1117/12.206950

KEYWORDS: Phase shifts, Photomasks, Phase shifting, Optical lithography, Excimer lasers, Semiconducting wafers, Reflectivity, Lithography, Optical simulations, Beam splitters

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Proceedings Article | 31 March 1995 Paper

Interferometric phase shift technique for high-resolution deep-UV microlithography

Frank Tittel, Joseph Cavallaro, Motoi Kido, Michael Smayling, Gabor Szabo, William Wilson

Proceedings Volume 2502, (1995) https://doi.org/10.1117/12.204981

KEYWORDS: Phase shifting, Photomasks, Phase shifts, Photoresist materials, Ultraviolet radiation, Interferometry, Optical lithography, Superposition, Deep ultraviolet, CCD cameras

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