Dr. Douglas J. Resnick Profile

Dr. Douglas J. Resnick

VP Marketing and Business Development at Canon Nanotechnologies Inc

SPIE Involvement:

Publications (93)

Proceedings Article | 1 December 2022 Presentation + Paper

Nanoimprint performance improvements for high volume semiconductor device manufacturing

Toshihiro Ifuku, Mitsuru Hiura, Yukio Takabayashi, Atsushi Kimura, Yoshio Suzaki, Toshiki Ito, Kiyohito Yamamoto, Byung Jin Choi, Teresa Estrada, Douglas Resnick

Proceedings Volume 12293, 122930E (2022) https://doi.org/10.1117/12.2643212

KEYWORDS: Nanoimprint lithography, Photomasks, Semiconducting wafers, Overlay metrology, Particles, Semiconductors, Optical lithography, Distortion, Logic

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Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL an attractive solution. Logic is more challenging from a defectivity perspective, often requiring defect levels significantly lower than memory devices that incorporate redundancy. In this paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. We specifically focus on performance improvements related to overlay and defectivity. For overlay, we present results on stability and also discuss new methods to further address high order distortion. For defectivity, we review random defect generation, particle adders and mask inspection methods. In addition, we also discuss Canon’s recent involvement in the New Energy and Industrial Technology Development Organization (NEDO) project and its goals related to logic devices. As a final topic, we describe Canon’s interests in fabrication beyond traditional advanced semiconductor devices.

SPIE Journal Paper | 8 March 2022 Open Access

Special Section Guest Editorial: Novel Patterning Technologies II

Douglas Resnick, Eric Panning

JM3, Vol. 21, Issue 01, 011001, (March 2022) https://doi.org/10.1117/12.10.1117/1.JMM.21.1.011001

KEYWORDS: Optical lithography, Nanoimprint lithography, Lithography, Nanotechnology, Wet etching, Semiconducting wafers, Silicon, Silica, Semiconductors, Satellites

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Proceedings Article | 27 June 2019 Paper

The advantages of nanoimprint lithography for semiconductor device manufacturing

Toshiya Asano, Keita Sakai, Kiyohito Yamamoto, Hiromi Hiura, Takahiro Nakayama, Tomohiko Hayashi, Yukio Takabayashi, Takehiko Iwanaga, Douglas Resnick

Proceedings Volume 11178, 111780I (2019) https://doi.org/10.1117/12.2532522

KEYWORDS: Photomasks, Nanoimprint lithography, Semiconducting wafers, Lithography, Optical lithography, Manufacturing, Semiconductors, Line width roughness, Particles, Semiconductor manufacturing

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Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Given the risks associated with this introduction, generally a combination of both performance and cost advantage is preferred. In this paper both performance attributes and cost are discussed. NIL resolution and linewidth roughness do not have the limitations of conventional projection lithographic method. Furthermore, it is not subject to patterning restrictions that forced the industry towards one dimensional patterning. A cost example case of 20nm dense contacts is also presented. Because NIL utilized a single step patterning approach, process costs are substantially reduced relative to ArF immersion lithography. Overall, NIL currently realizes a 28% cost advantage for this case, but as mask life continues to improve, the cost advantages become much more significant.

Proceedings Article | 26 March 2019 Paper

The advantages of nanoimprint lithography for semiconductor device manufacturing

Keita Sakai, Kiyohito Yamamoto, Hiromi Hiura, Takahiro Nakayama, Toshiya Asano, Tomohiko Hayashi, Yukio Takabayashi, Takehiko Iwanaga, Douglas Resnick

Proceedings Volume 10958, 109580G (2019) https://doi.org/10.1117/12.2514925

KEYWORDS: Photomasks, Nanoimprint lithography, Semiconducting wafers, Lithography, Optical lithography, Manufacturing, Semiconductors, Line width roughness, Particles, Semiconductor manufacturing

Read Abstract +

Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of widediameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Given the risks associated with this introduction, generally a combination of both performance and cost advantage is preferred. In this paper both performance attributes and cost are discussed. NIL resolution and linewidth roughness do not have the limitations of conventional projection lithographic method. Furthermore, it is not subject to patterning restrictions that forced the industry towards one dimensional patterning. A cost example case of 20nm dense contacts is also presented. Because NIL utilized a single step patterning approach, process costs are substantially reduced relative to ArF immersion lithography. Overall, NIL currently realizes a 28% cost advantage for this case, but as mask life continues to improve, the cost advantages become much more significant.

Proceedings Article | 3 October 2018 Paper

Nanoimprint lithography and a perspective on cost of ownership

Douglas Resnick, Junji Iwasa

Proceedings Volume 10810, 108100E (2018) https://doi.org/10.1117/12.2502757

KEYWORDS: Photomasks, Nanoimprint lithography, Semiconducting wafers, Optical lithography, Etching, Lithography, Deposition processes, Extreme ultraviolet lithography, Dry etching, Nanotechnology

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Proceedings Article | 16 October 2017 Paper

Development of an inkjet-enabled adaptive planarization process

Niyaz Khusnatdinov, Douglas Resnick, Shrawan Singhal, Michelle Grigas, S. V. Sreenivasan

Proceedings Volume 10451, 104511A (2017) https://doi.org/10.1117/12.2280311

KEYWORDS: Semiconducting wafers, Nanoimprint lithography, Photomasks, Optical lithography, Chemical mechanical planarization, Lithography, Manufacturing, Ultraviolet radiation

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Proceedings Article | 27 March 2017 Paper

Development of a robust reverse tone pattern transfer process

Niyaz Khusnatdinov, Gary Doyle, Douglas Resnick, Zhengmao Ye, Dwayne LaBrake, Brennan Milligan, Fred Alokozai, Jerry Chen

Proceedings Volume 10146, 101461A (2017) https://doi.org/10.1117/12.2260455

KEYWORDS: Atomic layer deposition, Photomasks, Lithography, Etching, Multilayers, Chromium, Silica, Oxides, Scanning electron microscopy, Photoresist processing, Semiconducting wafers, System on a chip, Critical dimension metrology, Plasma

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SPIE Journal Paper | 11 September 2015 Open Access

Special Section Guest Editorial: Alternative Lithographic Technologies IV

Douglas Resnick, Ricardo Ruiz, Hans Loeschner

JM3, Vol. 14, Issue 03, 031201, (September 2015) https://doi.org/10.1117/12.10.1117/1.JMM.14.3.031201

KEYWORDS: Lithography, Optical lithography, Nanofabrication, Extreme ultraviolet lithography, Nanotechnology, Nanoimprint lithography, Silver, Extreme ultraviolet, Integrated circuit design, Directed self assembly

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SPIE Journal Paper | 3 October 2014 Open Access

Special Section Guest Editorial: Alternative Lithographic Technologies

Douglas Resnick, Christopher Bencher, Ricardo Ruiz

JM3, Vol. 13, Issue 03, 031301, (October 2014) https://doi.org/10.1117/12.10.1117/1.JMM.13.3.031301

KEYWORDS: Lithography, Optical lithography, Electron beam lithography, Nanotechnology, Extreme ultraviolet lithography, Photomasks, Integrated circuit design, Double patterning technology, Nanolithography, Directed self assembly

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Proceedings Article | 28 March 2014 Paper

High volume nanoscale roll-based imprinting using jet and flash imprint lithography

Se Hyun Ahn, Michael Miller, Shuqiang Yang, Maha Ganapathisubramanian, Marlon Menezes, Vik Singh, Fen Wan, Jin Choi, Frank Xu, Dwayne LaBrake, Douglas Resnick, Paul Hofemann, S. Sreenivasan

Proceedings Volume 9049, 90490G (2014) https://doi.org/10.1117/12.2048172

KEYWORDS: Lithography, Polarizers, LCDs, Optical lithography, Aluminum, Etching, Transmittance, Nanostructures, Electron beam lithography, Organic light emitting diodes

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Proceedings Article | 28 March 2014 Paper

High-throughput jet and flash imprint lithography for advanced semiconductor memory

Niyaz Khusnatdinov, Zhengmao Ye, Kang Luo, Tim Stachowiak, Xiaoming Lu, J. Irving, Matt Shafran, Whitney Longsine, Matthew Traub, Van Truskett, Brian Fletcher, Weijun Liu, Frank Xu, Dwayne LaBrake, S. Sreenivasan

Proceedings Volume 9049, 904910 (2014) https://doi.org/10.1117/12.2048189

KEYWORDS: Photomasks, Lithography, Semiconducting wafers, Semiconductors, Ultraviolet radiation, Control systems, Printing, Photoresist processing, Silicon, Capillaries

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SPIE Journal Paper | 30 September 2013 Open Access

Special Section Guest Editorial: Alternative Lithographic Technologies

William Tong, Douglas Resnick, Ricardo Ruiz

JM3, Vol. 12, Issue 03, 031101, (September 2013) https://doi.org/10.1117/12.10.1117/1.JMM.12.3.031101

KEYWORDS: Lithography, High volume manufacturing, Extreme ultraviolet lithography, Optical lithography, Overlay metrology, Explosives, Metrology, Roads, Molecular self-assembly, Directed self assembly

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Proceedings Article | 26 September 2013 Paper

High volume nanoscale roll-based imprinting using jet and flash imprint lithography

Se Hyun Ahn, Mike Miller, Shuqiang Yang, Maha Ganapathisubramanian, Marlon Menezes, Vik Singh, Jin Choi, Frank Xu, Dwayne LaBrake, Douglas Resnick, S. V. Sreenivasan

Proceedings Volume 8816, 881602 (2013) https://doi.org/10.1117/12.2027765

KEYWORDS: Aluminum, Polarizers, Lithography, Ions, Etching, Transmission electron microscopy, Manufacturing, Nanostructures, Glasses, Opacity

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Proceedings Article | 9 September 2013 Paper

450mm wafer patterning with jet and flash imprint lithography

Ecron Thompson, Paul Hellebrekers, Paul Hofemann, Dwayne LaBrake, Douglas Resnick, S. Sreenivasan

Proceedings Volume 8880, 88800J (2013) https://doi.org/10.1117/12.2029275

KEYWORDS: Semiconducting wafers, Photomasks, Lithography, Optical lithography, Standards development, Metrology, Etching, Printing, Image processing, Ultraviolet radiation

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SPIE Journal Paper | 12 August 2013 Open Access

High-performance wire-grid polarizers using jet and Flash™ imprint lithography

Se Hyun Ahn, Shuqiang Yang, Mike Miller, Maha Ganapathisubramanian, Marlon Menezes, Jin Choi, Frank Xu, Douglas Resnick, S. Sreenivasan

JM3, Vol. 12, Issue 03, 031104, (August 2013) https://doi.org/10.1117/12.10.1117/1.JMM.12.3.031104

KEYWORDS: Polarizers, Lithography, Aluminum, Nanostructures, Opacity, Nanoimprint lithography, Optical lithography, Etching, Performance modeling, Glasses

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Proceedings Article | 26 March 2013 Paper

Defect reduction for semiconductor memory applications using jet and flash imprint lithography

Zhengmao Ye, Kang Luo, J. W. Irving, Xiaoming Lu, Wei Zhang, Brian Fletcher, Weijun Liu, Matt Shafran, Saul Lee, Whitney Longsine, Van Truskett, Frank Xu, Dwayne LaBrake, Douglas Resnick, S. Sreenivasan

Proceedings Volume 8680, 86800C (2013) https://doi.org/10.1117/12.2013694

KEYWORDS: Photomasks, Semiconducting wafers, Lithography, Particles, Neodymium, Semiconductors, Printing, Inspection, Ultraviolet radiation, Photoresist processing

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Proceedings Article | 26 March 2013 Paper

High performance wire grid polarizers using jet and flashTM imprint lithography

Sean Ahn, Jack Yang, Mike Miller, Maha Ganapathisubramanian, Marlon Menezes, Jin Choi, Frank Xu, Douglas Resnick, S. V. Sreenivasan

Proceedings Volume 8680, 86800W (2013) https://doi.org/10.1117/12.2013692

KEYWORDS: Polarizers, Lithography, Aluminum, Nanoimprint lithography, Etching, Nanostructures, Opacity, Ultraviolet radiation, Neodymium, Manufacturing

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The ability to pattern materials at the nanoscale can enable a variety of applications ranging from high density data storage, displays, photonic devices and CMOS integrated circuits to emerging applications in the biomedical and energy sectors. These applications require varying levels of pattern control, short and long range order, and have varying cost tolerances. Extremely large area roll to roll (R2R) manufacturing on flexible substrates is ubiquitous for applications such as paper and plastic processing. It combines the benefits of high speed and inexpensive substrates to deliver a commodity product at low cost. The challenge is to extend this approach to the realm of nanopatterning and realize similar benefits. The cost of manufacturing is typically driven by speed (or throughput), tool complexity, cost of consumables (materials used, mold or master cost, etc.), substrate cost, and the downstream processing required (annealing, deposition, etching, etc.). In order to achieve low cost nanopatterning, it is imperative to move towards high speed imprinting, less complex tools, near zero waste of consumables and low cost substrates. The Jet and Flash Imprint Lithography (J-FIL^TM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. In this paper we have developed a roll based J-FIL process and applied it to technology demonstrator tool, the LithoFlex 100, to fabricate large area flexible bilayer wire grid polarizers (WGP) and high performance WGPs on rigid glass substrates. Extinction ratios of better than 10000 were obtained for the glass-based WGPs. Two simulation packages were also employed to understand the effects of pitch, aluminum thickness and pattern defectivity on the optical performance of the WGP devices. It was determined that the WGPs can be influenced by both clear and opaque defects in the gratings, however the defect densities are relaxed relative to the requirements of a high density semiconductor device.

SPIE Journal Paper | 22 August 2012

Defect reduction for semiconductor memory applications using jet and flash imprint lithography

Zhengmao Ye, Kang Luo, Xiaoming Lu, Brian Fletcher, Weijun Liu, Frank Xu, Dwayne LaBrake, Douglas Resnick, S. Sreenivasan

JM3, Vol. 11, Issue 3, 031404, (August 2012) https://doi.org/10.1117/12.10.1117/1.JMM.11.3.031404

KEYWORDS: Photomasks, Particles, Semiconducting wafers, Lithography, Semiconductors, Inspection, Printing, Contamination, Manufacturing, Scanning electron microscopy

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SPIE Journal Paper | 9 August 2012 Open Access

Special Section Guest Editorial: Alternative Lithographic Technologies

William Tong, Douglas Resnick, Benjamen Rathsack

JM3, Vol. 11, Issue 3, 031401, (August 2012) https://doi.org/10.1117/12.10.1117/1.JMM.11.3.031401

KEYWORDS: Lithography, Optical lithography, Explosives, Nanoimprint lithography, Semiconductor manufacturing, Semiconductors, Optics manufacturing, Immersion lithography, Double patterning technology, Directed self assembly

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Proceedings Article | 21 March 2012 Paper

Roll-to-roll nanopatterning using jet and flash imprint lithography

Sean Ahn, Maha Ganapathisubramanian, Mike Miller, Jack Yang, Jin Choi, Frank Xu, Douglas Resnick, S. Sreenivasan

Proceedings Volume 8323, 83231L (2012) https://doi.org/10.1117/12.918040

KEYWORDS: Nanostructures, Lithography, Etching, Manufacturing, Optical lithography, Polarizers, Ultraviolet radiation, Data storage, Photonic devices, Integrated circuits

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The ability to pattern materials at the nanoscale can enable a variety of applications ranging from high density data storage, displays, photonic devices and CMOS integrated circuits to emerging applications in the biomedical and energy sectors. These applications require varying levels of pattern control, short and long range order, and have varying cost tolerances. Extremely large area R2R manufacturing on flexible substrates is ubiquitous for applications such as paper and plastic processing. It combines the benefits of high speed and inexpensive substrates to deliver a commodity product at low cost. The challenge is to extend this approach to the realm of nanopatterning and realize similar benefits. The cost of manufacturing is typically driven by speed (or throughput), tool complexity, cost of consumables (materials used, mold or master cost, etc.), substrate cost, and the downstream processing required (annealing, deposition, etching, etc.). In order to achieve low cost nanopatterning, it is imperative to move towards high speed imprinting, less complex tools, near zero waste of consumables and low cost substrates. The Jet and Flash Imprint Lithography (J-FIL^TM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. In this paper we address the key challenges for roll based nanopatterning by introducing a novel concept: Ink Jet based Roll-to-Roll Nanopatterning. To address this challenge, we have introduced a J-FIL based demonstrator product, the LithoFlex 100. Topics that are discussed in the paper include tool design and process performance. In addition, we have used the LithoFlex 100 to fabricate high performance wire grid polarizers on flexible polycarbonate (PC) films. Transmission of better than 80% and extinction ratios on the order of 4500 have been achieved.

Proceedings Article | 21 March 2012 Paper

Imprint process performance for patterned media at densities greater than 1Tb/in2

Zhengmao Ye, Scott Carden, Paul Hellebrekers, Dwayne LaBrake, Douglas Resnick, M. Melliar-Smith, S. Sreenivasan

Proceedings Volume 8323, 83230V (2012) https://doi.org/10.1117/12.918042

KEYWORDS: Lithography, Magnetism, Optical lithography, Photoresist processing, Beam propagation method, Etching, Silicon, Data storage, Semiconductors, Phase modulation

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Proceedings Article | 14 October 2011 Paper

Mask replication using jet and flash imprint lithography

Kosta Selinidis, Chris Jones, Gary Doyle, Laura Brown, Joseph Imhof, Dwayne LaBrake, Douglas Resnick, S. Sreenivasan

Proceedings Volume 8166, 816627 (2011) https://doi.org/10.1117/12.898865

KEYWORDS: Photomasks, Chromium, Etching, Lithography, Semiconductors, Semiconducting wafers, Particles, Optical lithography, Optical alignment, Inspection

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SPIE Journal Paper | 1 October 2011

Mask replication using jet and flash imprint lithography

Kosta Selinidis, Cynthia Brooks, Gary Doyle, Laura Brown, Chris Jones, Joseph Imhof, Dwayne LaBrake, Douglas Resnick, S. Sreenivasan

JM3, Vol. 10, Issue 04, 043005, (October 2011) https://doi.org/10.1117/12.10.1117/1.3646523

KEYWORDS: Photomasks, Chromium, Lithography, Etching, Electron beam lithography, Semiconductors, Semiconducting wafers, Inspection, Optical alignment, Silica

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SPIE Journal Paper | 1 July 2011

Defect reduction of high-density full-field patterns in jet and flash imprint lithography

Lovejeet Singh, Kang Luo, Zhengmao Ye, Frank Xu, Gaddi Haase, David Curran, Dwayne LaBrake, Douglas Resnick, S. Sreenivasan

JM3, Vol. 10, Issue 03, 033018, (July 2011) https://doi.org/10.1117/12.10.1117/1.3625635

KEYWORDS: Photomasks, Particles, Lithography, Semiconducting wafers, Nickel, Photoresist processing, Inspection, Contamination, Wafer inspection, Defect inspection

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Proceedings Article | 2 April 2011 Paper

Jet and flash imprint defectivity: assessment and reduction for semiconductor applications

Matt Malloy, Lloyd Litt, Steve Johnson, Douglas Resnick, David Lovell

Proceedings Volume 7970, 797006 (2011) https://doi.org/10.1117/12.881530

KEYWORDS: Inspection, Semiconducting wafers, Nanoimprint lithography, Particles, Semiconductors, Lithography, Glasses, Wafer inspection, Defect detection, Manufacturing

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Proceedings Article | 2 April 2011 Paper

High-density patterned media fabrication using jet and flash imprint lithography

Zhengmao Ye, Rick Ramos, Cynthia Brooks, Logan Simpson, John Fretwell, Scott Carden, Paul Hellebrekers, Dwayne LaBrake, Douglas Resnick, S. V. Sreenivasan

Proceedings Volume 7970, 79700L (2011) https://doi.org/10.1117/12.879932

KEYWORDS: Particles, Lithography, Optical lithography, Ozone, Coating, Tantalum, Manufacturing, Neodymium, Scanning electron microscopy, Ultraviolet radiation

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Proceedings Article | 2 April 2011 Paper

Progress in mask replication using jet and flash imprint lithography

Kosta Selinidis, Cynthia Brooks, Gary Doyle, Laura Brown, Chris Jones, Joseph Imhof, Dwayne LaBrake, Douglas Resnick, S.V. Sreenivasan

Proceedings Volume 7970, 797009 (2011) https://doi.org/10.1117/12.881647

KEYWORDS: Photomasks, Etching, Chromium, Lithography, Semiconductors, Inspection, Semiconducting wafers, Silica, Electron beam lithography, Optical alignment

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The Jet and Flash Imprint Lithography (J-FIL^TM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 10⁴ - 10⁵imprints. This suggests that tens of thousands of templates/masks will be required to satisfy the needs of a manufacturing environment. Electron-beam patterning is too slow to feasibly deliver these volumes, but instead can provide a high quality "master" mask which can be replicated many times with an imprint lithography tool. This strategy has the capability to produce the required supply of "working" templates/masks. In this paper, we review the development of the mask form factor, imprint replication tools and processes specifically for semiconductor applications. The requirements needed for semiconductors dictate the need for a well defined form factor for both master and replica masks which is also compatible with the existing mask infrastructure established for the 6025 semi standard, 6" x 6" x 0.25" photomasks. Complying with this standard provides the necessary tooling needed for mask fabrication processes, cleaning, metrology, and inspection. The replica form factor has additional features specific to imprinting such as a pre-patterned mesa. A Perfecta^TM MR5000 mask replication tool has been developed specifically to pattern replica masks from an e-beam written master. The system specifications include a throughput of four replicas per hour with an added image placement component of 5nm, 3sigma and a critical dimension uniformity error of less than 1nm, 3sigma. A new process has been developed to fabricate replicas with high contrast alignment marks so that designs for imprint can fit within current device layouts and maximize the usable printed area on the wafer. Initial performance results of this marks are comparable to the baseline fused silica align marks.

Proceedings Article | 2 April 2011 Paper

Defect reduction of high-density full-field patterns in jet and flash imprint lithography

Lovejeet Singh, Kang Luo, Zhengmao Ye, Frank Xu, Gaddi Haase, David Curran, Dwayne LaBrake, Douglas Resnick, S. V. Sreenivasan

Proceedings Volume 7970, 797007 (2011) https://doi.org/10.1117/12.879933

KEYWORDS: Photomasks, Particles, Lithography, Semiconducting wafers, Nickel, Inspection, Photoresist processing, Wafer inspection, Ultraviolet radiation, Defect inspection

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Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography (J-FIL) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned resist on the substrate. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the defect specifications of high end memory devices. Typical defectivity targets are on the order of 0.10/cm2. This work summarizes the results of defect inspections focusing on two key defect types; random non-fill defects occurring during the resist filling process and repeater defects caused by interactions with particles on the substrate. Non-fill defectivity must always be considered within the context of process throughput. The key limiting throughput step in an imprint process is resist filling time. As a result, it is critical to characterize the filling process by measuring non-fill defectivity as a function of fill time. Repeater defects typically have two main sources; mask defects and particle related defects. Previous studies have indicated that soft particles tend to cause non-repeating defects. Hard particles, on the other hand, can cause either resist plugging or mask damage. In this work, an Imprio 500 twenty wafer per hour (wph) development tool was used to study both defect types. By carefully controlling the volume of inkjetted resist, optimizing the drop pattern and controlling the resist fluid front during spreading, fill times of 1.5 seconds were achieved with non-fill defect levels of approximately 1.2/cm². Longevity runs were used to study repeater defects and a nickel contamination was identified as the key source of particle induced repeater defects.

Proceedings Article | 25 September 2010 Paper

Development of template and mask replication using jet and flash imprint lithography

Cynthia Brooks, Kosta Selinidis, Gary Doyle, Laura Brown, Dwayne LaBrake, Douglas Resnick, S. V. Sreenivasan

Proceedings Volume 7823, 78230O (2010) https://doi.org/10.1117/12.864332

KEYWORDS: Photomasks, Etching, Lithography, Semiconductors, Critical dimension metrology, Optical lithography, Inspection, Reactive ion etching, Silica, Chemistry

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SPIE Journal Paper | 1 July 2010

Cleaning of step-and-flash imprint masks with damage-free nonacid technology

Sherjang Singh, Ssuwei Chen, Kosta Selinidis, Brian Fletcher, Ian McMackin, Ecron Thompson, Douglas Resnick, Peter Dress, Uwe Dietze

JM3, Vol. 9, Issue 03, 033003, (July 2010) https://doi.org/10.1117/12.10.1117/1.3462815

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Proceedings Article | 25 May 2010 Paper

Defect reduction of patterned media templates and disks

Kang Luo, Steven Ha, John Fretwell, Rick Ramos, Zhengmao Ye, Gerard Schmid, Dwayne LaBrake, Douglas Resnick, S. Sreenivasan

Proceedings Volume 7748, 77480A (2010) https://doi.org/10.1117/12.866882

KEYWORDS: Particles, Inspection, Lithography, Ozone, Defect inspection, Servomechanisms, Tantalum, Manufacturing, Coating, Contamination

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Proceedings Article | 1 April 2010 Paper

Inspection of imprint lithography patterns for semiconductor and patterned media

Douglas Resnick, Gaddi Haase, Lovejeet Singh, David Curran, Gerard Schmid, Kang Luo, Cindy Brooks, Kosta Selinidis, John Fretwell, S. Sreenivasan

Proceedings Volume 7637, 76370R (2010) https://doi.org/10.1117/12.848391

KEYWORDS: Inspection, Photomasks, Lithography, Particles, Semiconducting wafers, Defect detection, Semiconductors, Optical inspection, Servomechanisms, Defect inspection

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Proceedings Article | 23 September 2009 Paper

Jet and flash imprint lithography for the fabrication of patterned media drives

Gerard Schmid, Cynthia Brooks, Zhengmao Ye, Steve Johnson, Dwayne LaBrake, S. V. Sreenivasan, Douglas Resnick

Proceedings Volume 7488, 748820 (2009) https://doi.org/10.1117/12.833366

KEYWORDS: Servomechanisms, Lithography, Magnetism, Inspection, Electron beam lithography, Optical lithography, Beam propagation method, Data storage, Head, Photoresist processing

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Proceedings Article | 23 September 2009 Paper

High-resolution e-beam repair for nanoimprint templates

Marcus Pritschow, Harald Dobberstein, Klaus Edinger, Mathias Irmscher, Douglas Resnick, Kosta Selinidis, Ecron Thompson, Markus Waiblinger

Proceedings Volume 7488, 74880V (2009) https://doi.org/10.1117/12.833030

KEYWORDS: Scanning electron microscopy, Etching, Electron beams, Semiconducting wafers, Metals, Manufacturing, Silicon, Nanoimprint lithography, Photomasks, Ultraviolet radiation

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Proceedings Article | 23 September 2009 Paper

Inspection of 32nm imprinted patterns with an advanced e-beam inspection system

Hong Xiao, Long Ma, Fei Wang, Yan Zhao, Jack Jau, Kosta Selinidis, Ecron Thompson, S. V. Sreenivasan, Douglas Resnick

Proceedings Volume 7488, 74881V (2009) https://doi.org/10.1117/12.833419

KEYWORDS: Inspection, Photomasks, Nanoimprint lithography, Electron beam lithography, Semiconducting wafers, Lithography, Defect inspection, Dysprosium, Scanning electron microscopy, Optical lithography

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Proceedings Article | 27 May 2009 Paper

Electron beam inspection methods for imprint lithography at 32 nm

Kosta Selinidis, Ecron Thompson, S. Sreenivasan, Douglas Resnick

Proceedings Volume 7470, 74700I (2009) https://doi.org/10.1117/12.835180

KEYWORDS: Photomasks, Inspection, Lithography, Metals, Scanning electron microscopy, Semiconducting wafers, Electron beam lithography, Wafer inspection, Defect detection, Image segmentation

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Proceedings Article | 11 May 2009 Paper

Inspection and repair for imprint lithography at 32 nm and below

Kosta Selinidis, Ecron Thompson, S. Sreenivasan, Douglas Resnick, Marcus Pritschow, Joerg Butschke, Mathias Irmscher, Holger Sailer, Harald Dobberstein

Proceedings Volume 7379, 73790N (2009) https://doi.org/10.1117/12.824264

KEYWORDS: Photomasks, Inspection, Metals, Defect detection, Lithography, Semiconducting wafers, Scanning electron microscopy, Ultraviolet radiation, Electron beams, Image segmentation

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Proceedings Article | 18 March 2009 Paper

High-resolution defect inspection of step-and-flash imprint lithography for 32-nm half-pitch patterning

Kosta Selinidis, Ecron Thompson, Ian McMackin, S.V. Sreenivasan, Douglas Resnick

Proceedings Volume 7271, 72711W (2009) https://doi.org/10.1117/12.815014

KEYWORDS: Photomasks, Inspection, Metals, Semiconducting wafers, Scanning electron microscopy, Defect detection, Lithography, Electron beam lithography, Defect inspection, Wafer inspection

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Proceedings Article | 18 March 2009 Paper

Automated imprint mask cleaning for step-and-flash imprint lithography

Sherjang Singh, Ssuwei Chen, Kosta Selinidis, Brian Fletcher, Ian McMackin, Ecron Thompson, Douglas Resnick, Peter Dress, Uwe Dietze

Proceedings Volume 7271, 72712H (2009) https://doi.org/10.1117/12.814290

KEYWORDS: Photomasks, Particles, Mask cleaning, Inspection, Lithography, Scanning electron microscopy, Photoresist processing, Nanoimprint lithography, Contamination, Semiconducting wafers

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Proceedings Article | 18 March 2009 Paper

Step and flash imprint lithography for manufacturing patterned media

Cynthia Brooks, Gerard Schmid, Mike Miller, Steve Johnson, Niyaz Khusnatdinov, Dwayne LaBrake, Douglas Resnick, S. V. Sreenivasan

Proceedings Volume 7271, 72711L (2009) https://doi.org/10.1117/12.815016

KEYWORDS: Magnetism, Optical lithography, Lithography, Silica, Chromium, Etching, Beam propagation method, Servomechanisms, Manufacturing, Data storage

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Proceedings Article | 17 October 2008 Paper

Evaluation of e-beam repair for nanoimprint templates

Marcus Pritschow, Volker Boegli, Joerg Butschke, Mathias Irmscher, Douglas Resnick, Holger Sailer, Kosta Selinidis, Ecron Thompson

Proceedings Volume 7122, 71222L (2008) https://doi.org/10.1117/12.801946

KEYWORDS: Etching, Quartz, Photomasks, Nanoimprint lithography, Opacity, Inspection, Ultraviolet radiation, Scanning electron microscopy, Phase shifts, Silicon

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Proceedings Article | 17 October 2008 Paper

Defect inspection of imprinted 32 nm half pitch patterns

Kosta Selinidis, Ecron Thompson, Ian McMackin, Joseph Perez, S. V. Sreenivasan, Douglas Resnick

Proceedings Volume 7122, 71222K (2008) https://doi.org/10.1117/12.801948

KEYWORDS: Photomasks, Inspection, Metals, Lithography, Semiconducting wafers, Scanning electron microscopy, Defect inspection, Etching, Image segmentation, Ultraviolet radiation

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Proceedings Article | 19 May 2008 Paper

Linewidth roughness characterization in step and flash imprint lithography

Gerard Schmid, Niyaz Khusnatdinov, Cynthia Brooks, Dwayne LaBrake, Ecron Thompson, Douglas Resnick

Proceedings Volume 7028, 70280A (2008) https://doi.org/10.1117/12.796015

KEYWORDS: Line width roughness, Photomasks, Critical dimension metrology, Electron beam lithography, Lithography, Etching, Semiconducting wafers, Scanning electron microscopy, Optical lithography, Line edge roughness

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Proceedings Article | 19 May 2008 Paper

32 nm imprint masks using variable shape beam pattern generators

Kosta Selinidis, Ecron Thompson, Gerard Schmid, Nick Stacey, Joseph Perez, John Maltabes, Douglas Resnick, Jeongho Yeo, Hoyeon Kim, Ben Eynon

Proceedings Volume 7028, 70280R (2008) https://doi.org/10.1117/12.793034

KEYWORDS: Semiconducting wafers, Line width roughness, Lithography, Etching, Photomasks, Critical dimension metrology, Beam shaping, Overlay metrology, Manufacturing, Line edge roughness

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Proceedings Article | 2 May 2008 Paper

Controlling linewidth roughness in step and flash imprint lithography

Gerard Schmid, Niyaz Khusnatdinov, Cynthia Brooks, Dwayne LaBrake, Ecron Thompson, Douglas Resnick, Jordan Owens, Arnie Ford, Shiho Sasaki, Nobuhito Toyama, Masaaki Kurihara, Naoya Hayashi, Hideo Kobayashi, Takashi Sato, Osamu Nagarekawa, Mark Hart, Kailash Gopalakrishnan, Rohit Shenoy, Ron Jih, Ying Zhang, Edmund Sikorski, Mary Beth Rothwell, Shusuke Yoshitake, Hitoshi Sunaoshi, Kenichi Yasui

Proceedings Volume 6792, 67920W (2008) https://doi.org/10.1117/12.798936

KEYWORDS: Line width roughness, Lithography, Critical dimension metrology, Etching, Semiconducting wafers, Line edge roughness, Chemically amplified resists, Vestigial sideband modulation, Optical lithography, Gaussian beams

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Proceedings Article | 21 March 2008 Paper

High resolution defect inspection of step and flash imprint lithography for 32 nm half-pitch patterning

I. McMackin, J. Perez, K. Selinidis, J. Maltabes, D. Resnick, S. Sreenivassan

Proceedings Volume 6921, 69211L (2008) https://doi.org/10.1117/12.773970

KEYWORDS: Photomasks, Inspection, Semiconducting wafers, Particles, Lithography, Defect inspection, Etching, Optical lithography, Image processing, Manufacturing

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Proceedings Article | 14 March 2008 Paper

Minimizing linewidth roughness for 22-nm node patterning with step-and-flash imprint lithography

Gerard Schmid, Niyaz Khusnatdinov, Cynthia Brooks, Dwayne LaBrake, Ecron Thompson, Douglas Resnick

Proceedings Volume 6921, 692109 (2008) https://doi.org/10.1117/12.772956

KEYWORDS: Line width roughness, Photomasks, Critical dimension metrology, Optical lithography, Etching, Electron beam lithography, Semiconducting wafers, Lithography, Scanning electron microscopy, Line edge roughness

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Proceedings Article | 6 February 2008 Paper

Step and flash imprint process integration techniques for photonic crystal patterning: template replication through wafer patterning irrespective of tone

Mike Miller, Cindy Brooks, David Lentz, Gary Doyle, Doug Resnick, Dwayne LaBrake

Proceedings Volume 6883, 68830D (2008) https://doi.org/10.1117/12.771302

KEYWORDS: Semiconducting wafers, Electron beam lithography, Photonic crystals, Manufacturing, Etching, Photomasks, Oxides, Optical lithography, Silica, Scanning electron microscopy

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Proceedings Article | 16 November 2007 Paper

Defect reduction progress in step and flash imprint lithography

K. Selenidis, J. Maltabes, I. McMackin, J. Perez, W. Martin, D. Resnick, S. Sreenivasan

Proceedings Volume 6730, 67300F (2007) https://doi.org/10.1117/12.747565

KEYWORDS: Inspection, Semiconducting wafers, Lithography, Particles, Defect inspection, Ultraviolet radiation, Contamination, Ions, Image processing, Wafer inspection

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Proceedings Article | 30 October 2007 Paper

Fabrication of nano-imprint templates for dual-Damascene applications using a high resolution variable shape E-beam writer

Marcus Pritschow, Joerg Butschke, Mathias Irmscher, Holger Sailer, Douglas Resnick, Ecron Thompson

Proceedings Volume 6730, 67300G (2007) https://doi.org/10.1117/12.742498

KEYWORDS: Overlay metrology, Quartz, Electron beam lithography, Etching, Metals, Chromium, Nanolithography, Vestigial sideband modulation, Scanning electron microscopy, Chemically amplified resists

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Proceedings Article | 30 October 2007 Paper

The development of full field high resolution imprint templates

Shusuke Yoshitake, Hitoshi Sunaoshi, Kenichi Yasui, Hideo Kobayashi, Takashi Sato, Osamu Nagarekawa, Ecron Thompson, Gerard Schmid, Douglas Resnick

Proceedings Volume 6730, 67300E (2007) https://doi.org/10.1117/12.747568

KEYWORDS: Photomasks, Etching, Chromium, Image processing, Lithography, Reticles, Optical proximity correction, Image resolution, Scanning electron microscopy, Silica

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Critical to the success of imprint lithography and Step and Flash Imprint Lithography (S-FIL^®) in particular is the manufacturing 1X templates. Several commercial mask shops now accept orders for 1X templates. Recently, there have been several publications addressing the fabrication of templates with 32nm and sub 32nm half pitch dimensions using high resolution Gaussian beam pattern generators. Currently, these systems are very useful for unit process development and device prototyping. In this paper, we address the progress made towards full field templates suitable for the fabrication of CMOS circuits. The starting photoplate consisted of a Cr hard mask (≤ 15nm) followed by a thin imaging layer of ZEP 520A. The EBM-5000 and the EBM-6000 variable shape beam pattern generators from NuFlare Technology were used to pattern the images on the substrates. Several key specifications of the EBM-6000, resulting in improved performance over the EBM-5000 include higher current density (70 A/cm²), astigmatism correction in the subfields, optimized variable stage speed control, and improved data handling to increase the maximum shot count limitation. To fabricate the template, the patterned resist serves as an etch mask for the thin Cr film. The Cr, in turn, is used as an etch block for the fused silica. A mesa is formed by etching the non-active areas using a wet buffered oxide etch (BOE) solution. The final step in the template process is a dice and polish step used to separate the plate into four distinct templates. Key steps in the fabrication process include the imaging and pattern processes. ZEP520A was chosen as the e-beam resist for its ability to resolve high resolution images. This paper documents the resolution and image placement capability with the processes described above. Although ZEP520A is slow relative to chemically amplified e-beam resists, it is only necessary to pattern 1/16^th the area relative to a 4X reduction mask. Write time calculations for 1X templates have also been performed, and are compared to 4X photomasks.

Proceedings Article | 14 May 2007 Paper

Three-dimensional template fabrication process for the dual damascene NIL approach

Joerg Butschke, Mathias Irmscher, Douglas Resnick, Holger Sailer, Ecron Thompson

Proceedings Volume 6607, 66070U (2007) https://doi.org/10.1117/12.728944

KEYWORDS: Etching, Photomasks, Quartz, Nanoimprint lithography, Photoresist processing, Electron beam lithography, Lithography, Printing, Chromium, Scanning electron microscopy

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Proceedings Article | 12 May 2007 Paper

Step and flash imprint lithography template fabrication for emerging market applications

Douglas Resnick, Gerard Schmid, Mike Miller, Gary Doyle, Chris Jones, Dwayne LaBrake

Proceedings Volume 6607, 66070T (2007) https://doi.org/10.1117/12.728943

KEYWORDS: Semiconducting wafers, Lithography, Photonic crystals, Etching, Silica, Electron beam lithography, Chromium, Silicon, Light emitting diodes, Polymethylmethacrylate

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Proceedings Article | 3 May 2007 Paper

Electron beam directed repair of fused silica imprint templates

Gerard Schmid, Douglas Resnick, Rainer Fettig, Klaus Edinger, Steven Young, William Dauksher

Proceedings Volume 6533, 65330P (2007) https://doi.org/10.1117/12.736921

KEYWORDS: Silica, Photomasks, Lithography, Etching, Electron beams, Scanning electron microscopy, Chromium, Atomic force microscopy, Nanoimprint lithography, Liquids

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Proceedings Article | 21 March 2007 Paper

A study of imprint-specific defects in the step and flash imprint lithography process

J. Perez, K. Selinidis, S. Johnson, B. Fletcher, F. Xu, J. Maltabes, I. McMackin, D. Resnick, S. Sreenivasan

Proceedings Volume 6517, 65170L (2007) https://doi.org/10.1117/12.720673

KEYWORDS: Particles, Inspection, Lithography, Semiconducting wafers, Manufacturing, Photomasks, Optical lithography, Ultraviolet radiation, Defect detection, Silica

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Researchers have demonstrated that imprint lithography techniques have remarkable replication resolution and can pattern sub-5nm structures. However, a fully capable lithography approach needs to address several challenges in order to be useful in manufacturing. For successful manufacturing insertion of Step and Flash Imprint Lithography (S-FILTM) into a broad set of applications such as photonics, magnetic storage, and integrated circuits (ICs), the following practical process related challenges need to be addressed: (i) Printing sub-50nm structures with non-uniform pattern densities: (ii) Precise alignment and overlay with the ability to mix-and-match with photolithography; (iii) Availability of 1X templates; (iv) Achieving appropriate throughput for acceptable cost of ownership; and (v) Minimizing template and imprint process-induced defects to allow acceptable process yields. The last challenge - the ability to achieve low defect densities - is desirable for all applications. However, it is one of the biggest challenges for S-FIL to be accepted in IC fabrication. This article specifically focuses on this last challenge and presents the current status of defect reduction in S-FIL technology. The article starts out by providing a brief background of S-FIL technology, and by including a discussion of the overall status of S-FIL technology in Section 1. Next, an overview of the experiments performed including the defect inspection approaches used is provided in Section 2. Section 3 introduces the classes of defects that are relevant to the S-FIL process. It also provides recent defect data for each of these classes. Section 4 presents defect data gathered over the last three years and provides defect reduction trends over this period. Section 5 discusses the topic of template lifetime. Finally Section 6 provides some concluding remarks. The defect data presented here is based on a large number of short-loop experiments based on optical inspection of templates and wafers; these data are complemented by a modest number of high resolution e-beam inspections to provide insight into S-FIL specific defects at leading edge line widths.

Proceedings Article | 16 March 2007 Paper

Whole wafer imprint patterning using step and flash imprint lithography: a manufacturing solution for sub-100-nm patterning

David Lentz, Gary Doyle, Mike Miller, Gerald Schmidt, Maha Ganapathisuramanian, Xiaoming Lu, Doug Resnick, Dwayne LaBrake

Proceedings Volume 6517, 65172F (2007) https://doi.org/10.1117/12.720671

KEYWORDS: Semiconducting wafers, Optical lithography, Etching, Lithography, Photomasks, Manufacturing, Silicon, Scanning electron microscopy, Electron beam lithography, Oxides

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Proceedings Article | 15 March 2007 Paper

Toward 22 nm for unit process development using step and flash imprint lithography

Gerard Schmid, Ecron Thompson, Nick Stacey, Douglas Resnick, Deirdre Olynick, Erik Anderson

Proceedings Volume 6517, 651717 (2007) https://doi.org/10.1117/12.718155

KEYWORDS: Lithography, Chromium, Photomasks, Etching, Semiconducting wafers, Electron beams, Critical dimension metrology, Silica, Optical lithography, Photoresist processing

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Proceedings Article | 13 February 2007 Paper

Manufacturing implications for photonic crystal patterning using imprint lithography

Chris Jones, David Lentz, Gary Doyle, Mike Miller, Maha Ganapathisubramanian, Xiaoming Lu, Doug Resnick, Dwayne LaBrake

Proceedings Volume 6486, 64860Q (2007) https://doi.org/10.1117/12.715220

KEYWORDS: Semiconducting wafers, Lithography, Photonic crystals, Light emitting diodes, Optical lithography, Etching, Manufacturing, Photomasks, Gallium nitride, Ultraviolet radiation

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Proceedings Article | 20 October 2006 Paper

Direct die-to-database electron-beam inspection of fused silica imprint templates

M. Tsuneoka, T. Hasebe, T. Tokumoto, C. Yan, M. Yamamoto, D. Resnick, E. Thompson, H. Wakamori, M. Inoue, Eric Ainley, Kevin Nordquist, William Dauksher

Proceedings Volume 6349, 63492D (2006) https://doi.org/10.1117/12.687196

KEYWORDS: Inspection, Silica, Semiconducting wafers, Metals, Lithography, Scanning electron microscopy, Photomasks, Chromium, Logic, Etching

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Proceedings Article | 23 March 2006 Paper

Defect inspection for imprint lithography using a die to database electron beam verification system

L. Jeff Myron, Ecron Thompson, Ian McMackin, Douglas Resnick, Tadashi Kitamura, Toshiaki Hasebe, Shinichi Nakazawa, Toshifumi Tokumoto, Eric Ainley, Kevin Nordquist, William Dauksher

Proceedings Volume 6151, 61510M (2006) https://doi.org/10.1117/12.659457

KEYWORDS: Inspection, Metals, Lithography, Silica, Logic, Semiconducting wafers, Defect detection, Photomasks, Chromium, Databases

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Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. Step and Flash Imprint Lithography (S-FIL^TM) is a unique method for printing sub-100nm geometries. Relative to other imprinting processes S-FIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. Further, S-FIL provides sub-100nm feature resolution without the significant expense of multielement, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. With respect to inspection, although defects as small as 70nm have been detected using optical techniques, it is clear that it will be necessary to take advantage of the resolution capabilities of electron beam inspection techniques. This paper reports the first systematic study of die-to-database electron beam inspection of patterns that were imprinted using an Imprio 250 system. The die-to-database inspection of the wafers was performed on an NGR2100 inspection system. Ultimately, the most desirable solution is to directly inspect the fused silica template. This paper also reports the results on the first initial experiments of direct inspection fused silica substrates at data rates of 200 MHz. Three different experiments were performed. In the first study, large (350-400nm) Metal 1 and contact features were imprinted and inspected as described above. Using a 12 nm pixel address grid, 24 nm defects were readily detected. The second experiment examined imprinted Metal 1 and Logic patterns with dimensions as small as 70nm. Using a pixel address of 3nm, and a defect threshold of 20 nm, a systematic study of the patterned arrays identified problem areas in the design of the pattern layout. Finally, initial inspection of 200mm fused silica patterned substrates has established proof of concept for direct inspection of imprint templates.

Proceedings Article | 6 May 2005 Paper

Indium tin oxide template development for step and flash imprint lithography

Kathleen Gehoski, Douglas Resnick, William Dauksher, Kevin Nordquist, Eric Ainley, Mark McCord, Mark Raphaelian, Harald Hess

Proceedings Volume 5751, (2005) https://doi.org/10.1117/12.606102

KEYWORDS: Chromium, Inspection, Etching, Lithography, Electron beams, Oxides, Indium, Tin, Quartz, Electron beam lithography

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Proceedings Article | 6 May 2005 Paper

Development of an etch-definable lift-off process for use with step and flash imprint lithography

Ngoc Le, Kathleen Gehoski, William Dauksher, Jeffrey Baker, Doug Resnick, Laura Dues

Proceedings Volume 5751, (2005) https://doi.org/10.1117/12.605932

KEYWORDS: Etching, Lithography, Oxides, Metals, Aluminum, Semiconducting wafers, Plasmas, Scanning electron microscopy, Silicon, Semiconductors

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Along with other Next Generation Lithography (NGL) methods, imprint lithography has been included on the International Roadmap for Semiconductors (ITRS) for the 32 nm node, predicted to be production-ready by 20131. Step and Flash Imprint Lithography (S-FIL) is one of the imprinting technologies being pursued due to its impressive imprinting capabilities, where imprinted features of less than 30 nm have been demonstrated. Unlike optical-based lithography, S-FIL uses techniques similar to that of contact printing, and thereby does not require complex and expensive optics and light sources to create images. Couple this with a reliable pattern transfer, and S-FIL could become a contender as a viable NGL technology. Similar to other imprint lithography systems, S-FIL printed features possess a residual layer several hundred angstroms thick, which requires a breakthrough etch prior to etching a subsequent layer. Of a greater concern, however, is the etch barrier used as the imaging layer for S-FIL. The present silicon content is limited to approximately nine percent, and the formulation is optimized for dispensing and achieving mechanical properties for the imprinting process. As a result, oxygen-based plasmas typically used for pattern transferring more conventional bi-layer structures are not compatible with the current S-FIL resist stack, and therefore pose a challenge from an etch perspective. The development of a recent etch process incorporating an ammonia-based plasma was a key enabler for pattern transfer, and ongoing development is being done to improve critical dimensions (CD). In this study, we examined a lift-off process using S-FIL. The material stacks with and without a "glue" layer will be discussed, and the challenges from imprinting to etch will be shared. Finally, the lift-off process will be used to demonstrate fabrication of a surface acoustic wave (SAW) device in addition to demonstrating patterning of a non-reactive metallization scheme such as Ti/Au.

Proceedings Article | 6 May 2005 Paper

Direct imprinting of dielectric materials for dual damascene processing

Michael Stewart, Jeffery Wetzel, Gerard Schmid, Frank Palmieri, Ecron Thompson, Eui Kyoon Kim, David Wang, Ken Sotodeh, Kane Jen, Stephen Johnson, Jianjun Hao, Michael Dickey, Yukio Nishimura, Richard Laine, Douglas Resnick, C. Willson

Proceedings Volume 5751, (2005) https://doi.org/10.1117/12.599977

KEYWORDS: Dielectrics, Silicon, Copper, Semiconducting wafers, Optical lithography, Etching, Lithography, Metals, Nanoimprint lithography, Plasma etching

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SPIE Journal Paper | 1 January 2005

Nanofabrication with step and flash imprint lithography

Michael Stewart, Stephen Johnson, Sidlgata Sreenivasan, Douglas Resnick, Carlton Willson

JM3, Vol. 4, Issue 01, 011002, (January 2005) https://doi.org/10.1117/12.10.1117/1.1862650

KEYWORDS: Lithography, Optical alignment, Photomasks, Nanoimprint lithography, Nanofabrication, Printing, Optical lithography, Etching, Overlay metrology, Polymers

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Proceedings Article | 6 December 2004 Paper

Inspection and repair issues for Step and Flash Imprint Lithography templates

Kevin Nordquist, William Dauksher, David Mancini, Douglas Resnick, Harald Hess, Donald Pettibone, David Adler, Kirk Bertsche, Roy White, Jeffrey Csuy, David Lee

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569846

KEYWORDS: Inspection, Scanning electron microscopy, Photomasks, Semiconducting wafers, Oxides, Lithography, Etching, Deep ultraviolet, Quartz, Atomic force microscopy

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Step and Flash Imprint Lithography (S-FIL) 1X templates must eventually achieve and maintain the very low defect counts commensurate to current production masks. This requires typically fewer than ten or even no defects over the entire field and to minimize template fabrication costs and techniques must be identified to repair defects on templates when they do occur. We describe inspection and repair methodologies and how it can be applied to the imprint template. For inspection, test patterns etched onto the template enable both a die-to-die comparison, to find nuisance defects, and also calibration of sensitivity to different types of preprogrammed defects. A state of the art deep UV photomask inspection system (KLA-Tencor model 526) can detect these events with about 70 nm threshold for imprint masks using reflection mode contrast. Initial scans are made at various stages of the imprint process: the processed mask, after dicing, and after several imprints. The scans show mostly isolated point defects at a density of ~ 10 to 100 per mm². To repair defects, studies were undertaken using RAVE’s nm650 tool which is essentially an AFM platform that relies upon a nano-machining technique for opaque defect removal. On S-FIL templates, the standard deviation for depth repairs in quartz from the target depth was found to be 3.1 nm (1σ). The spread in edge placement data for opaque line protrusions was 21.5 nm (1σ). Trench cuts through lines were successfully created with a minimum size of about 55nm. The repairs on the template were verified by imprinting the features on wafers. The range of depth offsets studied (-15 to +15) had no bearing on the imprinting process and the edge placement on wafers replicated the edge placement of the repaired templates. Trench cuts on the template were successfully filled with the imprint monomer and measured slightly larger than the minimum gap size. Finally, the imprinted wafers were used to pattern transfer features into 100nm of oxide.

Proceedings Article | 2 June 2004 Paper

Shaped beam technology for nano-imprint mask lithography

Peter Hudek, Dirk Beyer, Timothy Groves, Olaf Fortagne, William Dauksher, David Mancini, Kevin Nordquist, Douglas Resnick

Proceedings Volume 5504, (2004) https://doi.org/10.1117/12.568035

KEYWORDS: Electron beam lithography, Lithography, Photomasks, Photoresist processing, Etching, Chromium, Beam shaping, Nanotechnology, Image processing, Semiconducting wafers

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Proceedings Article | 20 May 2004 Paper

Sub-80-nm contact hole patterning using Step and Flash Imprint Lithography

David Mancini, Ngoc Le, Kathleen Gehoski, Steven Young, William Dauksher, Kevin Nordquist, Douglas Resnick

Proceedings Volume 5374, (2004) https://doi.org/10.1117/12.537382

KEYWORDS: Etching, Lithography, Silicon, Critical dimension metrology, Semiconducting wafers, Scanning electron microscopy, Quartz, Oxides, Photomasks, Printing

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Proceedings Article | 20 May 2004 Paper

Evaluation of the Imprio 100 Step and Flash Imprint Lithography tool

Kathleen Gehoski, David Mancini, Douglas Resnick

Proceedings Volume 5374, (2004) https://doi.org/10.1117/12.537380

KEYWORDS: Semiconducting wafers, Etching, Optical alignment, Lithography, Lamps, Nanoimprint lithography, Scanning electron microscopy, Overlay metrology, Manufacturing, Mercury

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Proceedings Article | 20 May 2004 Paper

Mesoscale modeling for SFIL simulating polymerization kinetics and densification

Ryan Burns, Stephen Johnson, Gerard Schmid, Eui Kim, Michael Dickey, Jason Meiring, Sean Burns, Nicholas Stacey, C. Grant Willson, Diana Convey, Yi Wei, Peter Fejes, Kathleen Gehoski, David Mancini, Kevin Nordquist, William Dauksher, Douglas Resnick

Proceedings Volume 5374, (2004) https://doi.org/10.1117/12.536216

KEYWORDS: Etching, Polymerization, Molecules, Monte Carlo methods, Finite element methods, Lithography, Ultraviolet radiation, Molecular interactions, Scanning electron microscopy, Optical lithography

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SPIE Journal Paper | 1 April 2004

Step and flash imprint lithography (S-FIL) is an attractive method for printing sub-100-nm geometries. Relative to other imprinting processes, S-FIL has the advantage of the template being transparent, thereby facilitating conventional overlay techniques.

Douglas Resnick, David Mancini, Kevin Nordquist, William Dauksher, Ian McMackin, Philip Schumaker, Ecron Thompson, S. Sreenivasan

JM3, Vol. 3, Issue 02, (April 2004) https://doi.org/10.1117/12.10.1117/1.1683261

KEYWORDS: Lithography, Printing, Etching, Semiconducting wafers, Photoresist processing, Image processing, Chromium, Distortion, Scanning electron microscopy, Silica

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Proceedings Article | 17 December 2003 Paper

Template fabrication for sub-80-nm contact hole patterning using step and flash imprint lithography

David Mancini, Kathleen Gehoski, William Dauksher, Kevin Nordquist, Douglas Resnick, Philip Schumaker, Ian McMackin

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518307

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Printing, Lithography, Etching, Photoresist processing, Cadmium, Scanning electron microscopy, Quartz, Electron beam lithography

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Proceedings Article | 16 June 2003 Paper

Analysis of critical dimension uniformity for Step and Flash imprint lithography

David Mancini, Kathleen Gehoski, William Dauksher, Kevin Nordquist, Douglas Resnick, Philip Schumaker, Ian McMackin

Proceedings Volume 5037, (2003) https://doi.org/10.1117/12.484923

KEYWORDS: Semiconducting wafers, Lithography, Critical dimension metrology, Scanning electron microscopy, Quartz, Etching, Cadmium, Photomasks, Chromium, Photoresist processing

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Proceedings Article | 16 June 2003 Paper

Advances in Step and Flash imprint lithography

Stephen Johnson, Todd Bailey, Michael Dickey, Britain Smith, Eunha Kim, Andrew Jamieson, Nicholas Stacey, John Ekerdt, C. Grant Willson, David Mancini, William Dauksher, Kevin Nordquist, Douglas Resnick

Proceedings Volume 5037, (2003) https://doi.org/10.1117/12.484985

KEYWORDS: Etching, Oxygen, Lithography, Polymerization, Silicon, Data modeling, Semiconducting wafers, Statistical analysis, Inspection, Materials processing

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Proceedings Article | 16 June 2003 Paper

Employing Step and Flash imprint lithography for gate-level patterning of a MOSFET device

Britain Smith, Nicholas Stacey, J. Donnelly, David Onsongo, Todd Bailey, Chris Mackay, Douglas Resnick, William Dauksher, David Mancini, Kevin Nordquist, S. Sreenivasan, Sanjay Banerjee, John Ekerdt, Grant Willson

Proceedings Volume 5037, (2003) https://doi.org/10.1117/12.490142

KEYWORDS: Etching, Lithography, Field effect transistors, Optical alignment, Semiconducting wafers, Optical lithography, Photomasks, Oxides, Reactive ion etching, Halogens

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Proceedings Article | 16 June 2003 Open Access

Imprint lithography: lab curiosity or the real NGL

Douglas Resnick, William Dauksher, David Mancini, Kevin Nordquist, Todd Bailey, Stephen Johnson, Nicholas Stacey, John Ekerdt, C. Grant Willson, S. Sreenivasan, Norman Schumaker

Proceedings Volume 5037, (2003) https://doi.org/10.1117/12.490126

KEYWORDS: Etching, Lithography, Semiconducting wafers, Silicon, Nanoimprint lithography, Chromium, Optical alignment, Image processing, Oxides, Inspection

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Proceedings Article | 27 December 2002 Paper

Image placement error due to pattern transfer for EUV masks

Zorian Masnyj, James Wasson, Bing Lu, Eric Weisbrod, Pawitter Mangat, Kevin Nordquist, Eric Ainley, William Dauksher, Douglas Resnick

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.477479

KEYWORDS: Photomasks, Extreme ultraviolet, Chromium, Distortion, Lithography, Extreme ultraviolet lithography, Etching, Image processing, Reticles, Semiconducting wafers

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Proceedings Article | 27 December 2002 Paper

Critical dimension and image placement issues for step and flash imprint lithography templates

Kevin Nordquist, David Mancini, William Dauksher, Eric Ainley, Kathleen Gehoski, Douglas Resnick, Zorian Masnyj, Pawitter Mangat

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.467753

KEYWORDS: Quartz, Chromium, Distortion, Overlay metrology, Lithography, Image processing, Photomasks, Critical dimension metrology, Fabrication, Etching

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SPIE Journal Paper | 1 October 2002

High resolution templates for step and flash imprint lithography

Douglas Resnick, William Dauksher, David Mancini, Kevin Nordquist, Eric Ainley, Kathleen Gehoski, Jeff Baker, Todd Bailey, B. Choi, Stephen Johnson, S. Sreenivasan, John Ekerdt, C. Grant Willson

JM3, Vol. 1, Issue 03, (October 2002) https://doi.org/10.1117/12.10.1117/1.1508410

KEYWORDS: Lithography, Scanning electron microscopy, Glasses, Printing, Overlay metrology, Distortion, Chromium, Photomasks, Solids, Defect inspection

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Proceedings Article | 30 July 2002 Paper

Bilayer and trilayer lift-off processing for i-line and DUV lithography

Laura Popovich, Kathleen Gehoski, David Mancini, Douglas Resnick

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474641

KEYWORDS: Photoresist processing, Metals, Deep ultraviolet, Lithography, Semiconducting wafers, Critical dimension metrology, Optical lithography, Reflectivity, Resistance, Etching

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Proceedings Article | 30 July 2002 Paper

Improved adhesion of photoresist to III-V substrates using PECVD carbon films

David Mancini, Steven Smith, Andrew Hooper, A. Talin, Daniel Chang, Douglas Resnick, Steven Voight

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474642

KEYWORDS: Carbon, Semiconducting wafers, Photonic integrated circuits, Gallium arsenide, Photoresist materials, Plasma enhanced chemical vapor deposition, Gallium, Arsenic, Deep ultraviolet, Head-mounted displays

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Proceedings Article | 24 July 2002 Paper

Sub-100 nm T-gates utilizing a single E-beam lithography exposure process

Eric Ainley, Scott Ageno, Kevin Nordquist, Douglas Resnick

Proceedings Volume 4690, (2002) https://doi.org/10.1117/12.474192

KEYWORDS: Photoresist processing, Polymethylmethacrylate, Metals, Electron beam lithography, Bridges, Coating, Monte Carlo methods, Resistance, Capacitance, Etching

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Proceedings Article | 24 July 2002 Paper

New methods for fabricating step and flash imprint lithography templates

Douglas Resnick, Todd Bailey, David Mancini, Kevin Nordquist, William Dauksher, Eric Ainley, A. Talin, Kathleen Gehoski, Jeff Baker, Byung Choi, Stephen Johnson, Matthew Colburn, Mario Meissl, S. Sreenivasan, John Ekerdt, C. Grant Willson

Proceedings Volume 4608, (2002) https://doi.org/10.1117/12.437269

KEYWORDS: Etching, Chromium, Oxides, Semiconducting wafers, Quartz, Glasses, Scanning electron microscopy, Lithography, Printing, Photomasks

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Proceedings Article | 24 July 2002 Paper

Low-cost nanostructure patterning using step and flash imprint lithography

S. Sreenivasan, C. Grant Willson, Norman Schumaker, Douglas Resnick

Proceedings Volume 4608, (2002) https://doi.org/10.1117/12.437804

KEYWORDS: Lithography, Extreme ultraviolet, Optical lithography, Photomasks, Inspection, Semiconducting wafers, Extreme ultraviolet lithography, Nanostructures, Microelectronics, Manufacturing

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Proceedings Article | 1 July 2002 Paper

Cost of ownership analysis for patterning using step and flash imprint lithography

S. Sreenivasan, C. Grant Willson, Norman Schumaker, Douglas Resnick

Proceedings Volume 4688, (2002) https://doi.org/10.1117/12.472275

KEYWORDS: Lithography, Extreme ultraviolet, Optical lithography, Photomasks, Inspection, Semiconducting wafers, Microelectronics, Extreme ultraviolet lithography, Manufacturing, Etching

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Proceedings Article | 1 July 2002 Paper

High-resolution templates for step and flash imprint lithography

Douglas Resnick, William Dauksher, David Mancini, Kevin Nordquist, Eric Ainley, Kathleen Gehoski, Jeff Baker, Todd Bailey, Byung Choi, Stephen Johnson, S. Sreenivasan, John Ekerdt, C. Grant Willson

Proceedings Volume 4688, (2002) https://doi.org/10.1117/12.472293

KEYWORDS: Etching, Quartz, Chromium, Scanning electron microscopy, Photomasks, Semiconducting wafers, Glasses, Lithography, Printing, Oxides

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Proceedings Article | 3 October 2001 Paper

Low surface energy polymeric release coating for improved contact print lithography

David Mancini, Douglas Resnick, Kathleen Gehoski, Laura Popovich, Daniel Chang

Proceedings Volume 4562, (2001) https://doi.org/10.1117/12.458339

KEYWORDS: Photomasks, Coating, Atrial fibrillation, Semiconducting wafers, Printing, Lithography, Polymers, Scanning electron microscopy, Photoresist materials, Particles

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Contact printing has been used for decades in many various lithography applications in the microelectronic industry. While vacuum contact printing processes offer sub-micron resolution and high throughput, they often suffer from some important drawbacks. One of the most common problems is degradation in both resolution and defect density which occurs when the same mask si used for multiple exposures without frequent mask cleans. This is largely due to the relatively high surface energy of both quartz and chrome and the tendency of most photoresists to adhere to these surfaces. As a result, when a mask and wafer are pressed into intimate contact, resist will tend to stick to the mask creating a defect on the wafer, effectively propagating defects to subsequent wafers. In this study, DuPont Teflon AF 1601S is used as a photomask coating and evaluated for its ability to act as a release agent and reduce defects while maintaining resolution for multiple exposures. Teflon AF is an amorphous, transparent, low surface energy, polymeric material that can be spin coated into a thin conformal film. Tests have shown that when using an uncoated mask in vacuum contact, resolution of 0.75 micrometers dense lines is severely degraded after less than 10 consecutive exposures. However, when the mask is coated, 0.75 micrometers dense lines were successfully resolved using vacuum contact for over 200 exposures without cleaning. In addition, it has been demonstrated that Teflon AF coatings impart to a mask a self-cleaning capability, since particles tend to stick to the photoresist rather than the mask. A coated mask, which was purposefully contaminated with particulates, resolved 0.75 micrometers dense lines on all but the first wafer of a series of 25 consecutive exposures. The patented mask releases layer process has successfully been demonstrated with a positive novolak resist. Additional data which describes the system chemistry, dilution and coating process, and film morphology are also presented.

Proceedings Article | 20 August 2001 Paper

Evaluation of Shipley XP2040D positive chemically amplified resist for SCALPEL mask fabrication

Bing Lu, Zorian Masnyj, Pawitter Mangat, Kevin Nordquist, Eric Ainley, Douglas Resnick

Proceedings Volume 4343, (2001) https://doi.org/10.1117/12.436703

KEYWORDS: Critical dimension metrology, Photomasks, Charged-particle lithography, Mask making, Silicon, Line edge roughness, Photoresist processing, Chemically amplified resists, Semiconducting wafers, Scanning electron microscopy

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Proceedings Article | 22 January 2001 Paper

UV inspection of EUV and SCALPEL reticles

Donald Pettibone, Noah Bareket, Ted Liang, Alan Stivers, Scott Hector, Pawitter Mangat, Douglas Resnick, Michael Lercel, Mark Lawliss, Christopher Magg, Anthony Novembre, Reginald Farrow

Proceedings Volume 4186, (2001) https://doi.org/10.1117/12.410699

KEYWORDS: Photomasks, Inspection, Charged-particle lithography, Extreme ultraviolet, Reticles, Reflectivity, Semiconducting wafers, Silicon, Ultraviolet radiation, Chromium

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Proceedings Article | 21 July 2000 Paper

Evaluation of negative DUV resist UVN30 for electron-beam exposure of NGL masks

Zorian Masnyj, Pawitter Mangat, Eric Ainley, Kevin Nordquist, Douglas Resnick

Proceedings Volume 3997, (2000) https://doi.org/10.1117/12.390090

KEYWORDS: Critical dimension metrology, Photomasks, Line edge roughness, Mask making, Deep ultraviolet, Thin film coatings, Photoresist processing, Lithography, Semiconducting wafers, Manufacturing

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Proceedings Article | 25 June 1999 Paper

Advanced negative i-line resist development on metal surfaces for next-generation lithography mask fabrication

Craig Ghelli, David Mancini, Douglas Resnick, Pawitter Mangat, William Dauksher

Proceedings Volume 3676, (1999) https://doi.org/10.1117/12.351117

KEYWORDS: Metals, Extreme ultraviolet lithography, Antireflective coatings, Silicon, Lithography, Charged-particle lithography, Mask making, Photomasks, Semiconducting wafers, Scanning electron microscopy

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Proceedings Article | 7 July 1997 Paper

SNR200 chemically amplified resist optimization

Janet Rocque, Denise Puisto, Douglas Resnick, Kevin Cummings, William Chu, Philip Seese

Proceedings Volume 3048, (1997) https://doi.org/10.1117/12.275799

KEYWORDS: Photoresist processing, Photomasks, X-rays, X-ray lithography, Semiconducting wafers, Critical dimension metrology, Lithography, Silicon, Chemically amplified resists, Gold

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Proceedings Article | 27 May 1996 Paper

Development of two new positive DUV photoresists for use with direct-write e-beam lithography

David Mancini, Douglas Resnick, Kevin Nordquist, William Dauksher, James Thackeray, Mark McCord

Proceedings Volume 2723, (1996) https://doi.org/10.1117/12.240461

KEYWORDS: Ultraviolet radiation, Semiconducting wafers, Deep ultraviolet, Etching, Electron beam lithography, Photoresist materials, Lithography, Silicon, Photoresist processing, Polymers

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Proceedings Article | 24 June 1993 Paper

Accelerated radiation damage testing of x-ray mask membrane materials

Philip Seese, Kevin Cummings, Douglas Resnick, Arnold Yanof, William Johnson, Gregory Wells, John Wallace

Proceedings Volume 1924, (1993) https://doi.org/10.1117/12.146527

KEYWORDS: Silicon carbide, X-rays, Silicon, Radiation effects, Diamond, Photons, Metrology, Mirrors, Chlorine, Boron

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Showing 5 of 93 publications

Proceedings Volume Editor (5)

SPIE Conference Volume | 21 April 2015

Alternative Lithographic Technologies VII

SPIE Conference Volume | 30 April 2014

Alternative Lithographic Technologies VI

SPIE Conference Volume | 11 April 2013

Alternative Lithographic Technologies V

SPIE Conference Volume | 18 April 2012

Alternative Lithographic Technologies IV

SPIE Conference Volume | 1 May 1990

Electron-Beam, X-Ray, and Ion-Beam Technology: Submicrometer Lithographies IX

Conference Committee Involvement (33)

Photomask Technology 2025

21 September 2025 | Monterey, California, United States

Novel Patterning Technologies 2025

24 February 2025 | San Jose, California, United States

Photomask Technology 2024

30 September 2024 | Monterey, California, United States

Novel Patterning Technologies 2024

26 February 2024 | San Jose, California, United States

Photomask Technology 2023

2 October 2023 | Monterey, California, United States

Novel Patterning Technologies 2023

27 February 2023 | San Jose, California, United States

Photomask Technology 2022

26 September 2022 | Monterey, California, United States

Novel Patterning Technologies 2022

25 April 2022 | San Jose, California, United States

Photomask Technology

27 September 2021 | Online Only, United States

Novel Patterning Technologies 2021

22 February 2021 | Online Only, California, United States

Photomask Technology

21 September 2020 | Online Only, California, United States

Novel Patterning Technologies for Semiconductors, MEMS/NEMS and MOEMS 2020

24 February 2020 | San Jose, California, United States

Photomask Technology

16 September 2019 | Monterey, California, United States

Novel Patterning Technologies for Semiconductors, MEMS/NEMS and MOEMS 2019

25 February 2019 | San Jose, California, United States

Photomask Technology

17 September 2018 | Monterey, California, United States

Novel Patterning Technologies 2018

26 February 2018 | San Jose, California, United States

Photomask Technology

11 September 2017 | Monterey, California, United States

Emerging Patterning Technologies 2017

27 February 2017 | San Jose, California, United States

Alternative Lithographic Technologies VIII

22 February 2016 | San Jose, California, United States

Extreme Ultraviolet (EUV) Lithography VII

22 February 2016 | San Jose, California, United States

Alternative Lithographic Technologies VII

23 February 2015 | San Jose, California, United States

Photomask Technology 2014

16 September 2014 | Monterey, California, United States

Alternative Lithographic Technologies VI

24 February 2014 | San Jose, California, United States

SPIE Photomask Technology

10 September 2013 | Monterey, California, United States

Alternative Lithographic Technologies V

25 February 2013 | San Jose, California, United States

Photomask Technology

11 September 2012 | Monterey, California, United States

Alternative Lithographic Technologies IV

13 February 2012 | San Jose, California, United States

Photomask Technology

19 September 2011 | Monterey, California, United States

Alternative Lithographic Technologies III

1 March 2011 | San Jose, California, United States

Alternative Lithographic Technologies II

23 February 2010 | San Jose, California, United States

Alternative Lithographic Technologies

24 February 2009 | San Jose, California, United States

Emerging Lithographic Technologies XII

26 February 2008 | San Jose, California, United States

Electron-Beam, X-Ray, and Ion-Beam Technology: Submicrometer Lithographies IX

7 March 1990 | San Jose, CA, United States

Showing 5 of 33 Conference Committees

Course Instructor

SC622: Nano-Scale Patterning with Imprint Lithography

This course will start by discussing the basics of nanoimprint lithography including a discussion of the various kinds of imprint lithography. It will cover advantages and challenges of using imprint lithography for sub-100 nm and sub-50 nm patterning. The course will focus on step and repeat UV nanoimprint lithography tools and processes. Specific topics addressed will include: tool design and performance, process resolution limits, CD control, etch requirements, overlay alignment, process defects, materials development, and 1X mask infrastructure. Potential applications of the technology will also be discussed.

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